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(parent: 11741d5) | patch
Fixes for addv and xtn2 instructions.
authorJim Wilson <jim.wilson@linaro.org>
Wed, 18 Jan 2017 00:01:40 +0000 (16:01 -0800)
committerJim Wilson <jim.wilson@linaro.org>
Wed, 18 Jan 2017 00:11:09 +0000 (16:11 -0800)
commit05b3d79d265aa9de2a81ac2d0f5e6f5821161f34
treee6e003e2f85da81fdc73ee6a4b209170a2ada370tree | snapshot
parent11741d50eff1424bb1f628ede3dfe42a74343b52commit | diff
Fixes for addv and xtn2 instructions.

sim/aarch64/
* simulator.c (do_vec_ADDV): Call aarch64_set_vec_u64 instead of
aarch64_set_reg_u64.  In case 2, call HALT_UNALLOC if not full.  In
case 3, call HALT_UNALLOC unconditionally.
(do_vec_XTN): Delete shifts.  In case 2, change index from i + 4 to
i + 2.  Delete if on bias, change index to i + bias * X.

sim/testsuite/sim/aarch64/
* addv.s: New.
* xtn.s: New.
sim/aarch64/ChangeLog diff | blob | history
sim/aarch64/simulator.c diff | blob | history
sim/testsuite/sim/aarch64/ChangeLog diff | blob | history
sim/testsuite/sim/aarch64/addv.s [new file with mode: 0644] blob
sim/testsuite/sim/aarch64/xtn.s [new file with mode: 0644] blob
Domain: System / Toolchain;