[RISCV][InsertVSETVLI] Using right instruction during mutate AVL of vsetvli

[RISCV][InsertVSETVLI] Using right instruction during mutate AVL of vsetvli

Fixing a crash during vsetvli insertion pass.

We have a testcase with 3 vsetvli:

1. vsetivli        zero, 2, e8, m4, ta, ma
2. li      a1, 32;  vsetvli zero, a1, e8, m4, ta, mu
3. vsetivli        zero, 2, e8, m4, ta, ma

and then we trying to optimize 2nd vsetvli since the only user is vmv.x.s, so
it could mutate the AVL operand to the AVL operand of the 3rd vsetvli.
OK, so we propagate 2 to vsetvli, BUT it's vsetvli not vsetivli, so it expect a
register rather than a immediate value, so we have to update the opcode
if needed.

Reviewed By: reames

Differential Revision: https://reviews.llvm.org/D141061