Align arm64 data section as requested (#71044)

Align arm64 data section as requested (#71044)

* Align arm64 data section as requested

Currently, the data section alignment request is ignored unless
it is 8. Since the minimum is 4, this effectively means that
16-byte SIMD16 data alignment requests are ignored. This is likely
because this code was written before arm64 supported SIMD, and was
never revised.

Cases of SIMD loads of constant data lead to larger alignment
padding of the data section. This is somewhat mitigated by
https://github.com/dotnet/runtime/pull/71043 which fixes a bug with overallocation
and overalignment of SIMD8 data loads.

* Additional fixes

1. On arm64/LA64, if asking for a data alignment greater than code
alignment, we need to increase the requested code alignment since
the code section is where this data will live. This isn't viewable
in SPMI diffs, but it does increase the alignment of some functions
from 8 to 16 byte code alignment.
2. Assert that the data section is at least 4 bytes aligned
(this is the default in our code, and alignment only increases).
3. Simplify the code setting the alignment flags for allocMem.

* Formatting + disable alignment asserts

It looks like the buffer pointer passed back from crossgen2 doesn't
meet the alignment request. Perhaps it does in the final image, but
not in the buffer the JIT fills in? Maybe the asserts could be used
for JIT-time but not AOT (when the buffer address is the final location
of the code/data)?