[AMDGPU] Add and update scalar instructions
authorGraham Sellers <graham.sellers@amd.com>
Thu, 29 Nov 2018 16:05:38 +0000 (16:05 +0000)
committerGraham Sellers <graham.sellers@amd.com>
Thu, 29 Nov 2018 16:05:38 +0000 (16:05 +0000)
commit04f7a4d2d214356abc722b0232f7e2e3b1495379
tree1edfb4ccf7a12780216e4e8d3dfed7452621e243
parent535c1af0bf906d8a13f42b33953ede634b31878c
[AMDGPU] Add and update scalar instructions

This patch adds support for S_ANDN2, S_ORN2 32-bit and 64-bit instructions and adds splits to move them to the vector unit (for which there is no equivalent instruction). It modifies the way that the more complex scalar instructions are lowered to vector instructions by first breaking them down to sequences of simpler scalar instructions which are then lowered through the existing code paths. The pattern for S_XNOR has also been updated to apply inversion to one input rather than the output of the XOR as the result is equivalent and may allow leaving the NOT instruction on the scalar unit.

A new tests for NAND, NOR, ANDN2 and ORN2 have been added, and existing tests now hit the new instructions (and have been modified accordingly).

Differential: https://reviews.llvm.org/D54714
llvm-svn: 347877
12 files changed:
llvm/lib/Target/AMDGPU/AMDGPUInstructions.td
llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
llvm/lib/Target/AMDGPU/SIInstrInfo.h
llvm/lib/Target/AMDGPU/SOPInstructions.td
llvm/test/CodeGen/AMDGPU/andorn2.ll [new file with mode: 0644]
llvm/test/CodeGen/AMDGPU/constant-fold-mi-operands.ll
llvm/test/CodeGen/AMDGPU/fceil64.ll
llvm/test/CodeGen/AMDGPU/ftrunc.f64.ll
llvm/test/CodeGen/AMDGPU/insert_vector_elt.ll
llvm/test/CodeGen/AMDGPU/nand.ll [new file with mode: 0644]
llvm/test/CodeGen/AMDGPU/nor.ll [new file with mode: 0644]
llvm/test/CodeGen/AMDGPU/xnor.ll