[X86][Costmodel] Load/store i16 Stride=3 VF=4 interleaving costs
authorRoman Lebedev <lebedev.ri@gmail.com>
Sun, 3 Oct 2021 20:37:13 +0000 (23:37 +0300)
committerRoman Lebedev <lebedev.ri@gmail.com>
Sun, 3 Oct 2021 20:39:51 +0000 (23:39 +0300)
commit04f1469cb4caeedaabc3ab0f9ae00a8576f774eb
tree9a48812688029ca1ad62d9bb93d160f4964c6c86
parent8e8fb77aa40c287067306df7ff2416122b31e33b
[X86][Costmodel] Load/store i16 Stride=3 VF=4 interleaving costs

The only sched models that for cpu's that support avx2
but not avx512 are: haswell, broadwell, skylake, zen1-3

For load we have:
https://godbolt.org/z/sP4j1173f - for intels `Block RThroughput: =7.0`; for ryzens, `Block RThroughput: <=3.0`
So pick cost of `7`.

For store we have:
https://godbolt.org/z/sP4j1173f - for intels `Block RThroughput: =6.0`; for ryzens, `Block RThroughput: <=2.0`
So pick cost of `6`.

I'm directly using the shuffling asm the llc produced,
without any manual fixups that may be needed
to ensure sequential execution.

Reviewed By: RKSimon

Differential Revision: https://reviews.llvm.org/D111015
llvm/lib/Target/X86/X86TargetTransformInfo.cpp
llvm/test/Analysis/CostModel/X86/interleaved-load-i16-stride-3.ll
llvm/test/Analysis/CostModel/X86/interleaved-store-i16-stride-3.ll