[RISCV] Add isel patterns to select vsub_vx intrinsic to vadd.vi if it uses a small...
authorCraig Topper <craig.topper@sifive.com>
Wed, 31 Mar 2021 16:22:38 +0000 (09:22 -0700)
committerCraig Topper <craig.topper@sifive.com>
Wed, 31 Mar 2021 16:26:41 +0000 (09:26 -0700)
commit04f10ab367b5c547f5de3285890e74146a5949b0
tree66d8538292a95a075307c232172cff520ef4e0db
parent09b2419360e1bf35037fc7b4299074150e8e68a5
[RISCV] Add isel patterns to select vsub_vx intrinsic to vadd.vi if it uses a small enough immediate

Also modify the simm5_plus1 check because Imm-1 is UB if Imm happens
to be INT64_MIN. I don't think the compiler would optimize based on that in this
usage, but it could fail UBSan or -ftrapv.

Reviewed By: HsiangKai, frasercrmck

Differential Revision: https://reviews.llvm.org/D99637
llvm/lib/Target/RISCV/RISCVInstrInfoV.td
llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
llvm/test/CodeGen/RISCV/rvv/vsub-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vsub-rv64.ll