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drm/amdgpu/gfx10: add updated GOLDEN_TSC_COUNT_UPPER/LOWER register offsets for VGH
authorchen gong <curry.gong@amd.com>
Fri, 8 Jan 2021 04:46:44 +0000 (12:46 +0800)
committerAlex Deucher <alexander.deucher@amd.com>
Thu, 14 Jan 2021 05:24:52 +0000 (00:24 -0500)
commit04eb6e773e9f3167a5921d74e8ad99cdcc4166c3
tree8b84a621b4a958f7fedcb7c9eb304dd6e47ba385tree | snapshot
parent8b335bff643f3b39935c7377dbcd361c5b605d98commit | diff
drm/amdgpu/gfx10: add updated GOLDEN_TSC_COUNT_UPPER/LOWER register offsets for VGH

The address of the GOLDEN_TSC_COUNT_UPPER/GOLDEN_TSC_COUNT_LOWER for
Vnagogh are different from the others.

The offset of the GOLDEN_TSC_COUNT_UPPER for Vangogh is 0x0025 by
calculation.
The offset of the GOLDEN_TSC_COUNT_LOWER for Vangogh is 0x0026 by
calculation.

Signed-off-by: chen gong <curry.gong@amd.com>
Acked-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c diff | blob | history
Domain: System / Kernel;