projects / platform / upstream / llvm.git / commit
? search:
summary | shortlog | log | commit | commitdiff | tree
(parent: 98d763a) | patch
[RISCV] Refactor FeatureRVCHints to make ProcessorModel more intuitive
authorZakk Chen <zakk.chen@sifive.com>
Thu, 30 Apr 2020 10:24:19 +0000 (03:24 -0700)
committerZakk Chen <zakk.chen@sifive.com>
Fri, 10 Jul 2020 06:07:39 +0000 (23:07 -0700)
commit04b9a46c842f793a2baedcad64de35fcbd3e93b7
treed58d04b637e31bdf77ffcd490b9e9e84455527e0tree | snapshot
parent98d763ad051f5eab89fa46167516fc8a84f471d0commit | diff
[RISCV] Refactor FeatureRVCHints to make ProcessorModel more intuitive

Reviewers: luismarques, asb, evandro

Reviewed By: asb, evandro

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D77030
llvm/lib/Target/RISCV/RISCV.td diff | blob | history
llvm/lib/Target/RISCV/RISCVSubtarget.h diff | blob | history
llvm/test/MC/RISCV/rv32c-invalid.s diff | blob | history
Domain: System / Toolchain;