[RISCV] Group the legal vector types into lists we can iterator over in the RISCVISel...
authorCraig Topper <craig.topper@sifive.com>
Wed, 27 Jan 2021 17:48:27 +0000 (09:48 -0800)
committerCraig Topper <craig.topper@sifive.com>
Wed, 27 Jan 2021 18:20:12 +0000 (10:20 -0800)
commit04570e98c85f7cd35577f8193ac04ecd3bc38fea
treed24994f5dbb281d2cf519064a42012cf7c9959f7
parentf30c523660106dd19072ae7baed72b18adfb0aa7
[RISCV] Group the legal vector types into lists we can iterator over in the RISCVISelLowering constructor

Remove the RISCVVMVTs namespace because I don't think it provides
a lot of value. If we change the mappings we'd likely have to add
or remove things from the list anyway.

Add a wrapper around addRegisterClass that can determine the
register class from the fixed size of the type.

Reviewed By: frasercrmck, rogfer01

Differential Revision: https://reviews.llvm.org/D95491
llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
llvm/lib/Target/RISCV/RISCVISelLowering.cpp