drm/i915/resets: Don't set / test for per-engine reset bits with GuC submission
authorMatthew Brost <matthew.brost@intel.com>
Thu, 28 Oct 2021 22:42:24 +0000 (15:42 -0700)
committerJohn Harrison <John.C.Harrison@Intel.com>
Tue, 9 Nov 2021 21:54:24 +0000 (13:54 -0800)
commit03f060b73f9ad9555f6251cac21c692df8112a68
tree74d85f675957f333424a9e305ae72825c5c9e722
parentc10a652e239e21492525fab295dc2fc303338ef1
drm/i915/resets: Don't set / test for per-engine reset bits with GuC submission

Don't set, test for, or clear per-engine reset bits with GuC submission
as the GuC owns the per engine resets not the i915. Setting, testing
for, and clearing these bits is causing issues with the hangcheck
selftest. Rather than change to test to not use these bits, rip the use
of these bits out from the reset code.

Signed-off-by: Matthew Brost <matthew.brost@intel.com>
Reviewed-by: John Harrison <John.C.Harrison@Intel.com>
Signed-off-by: John Harrison <John.C.Harrison@Intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20211028224224.32693-1-matthew.brost@intel.com
drivers/gpu/drm/i915/gt/intel_reset.c