[AArch64] Match instruction "STP with base register" in prologue
authorYao Qi <yao.qi@linaro.org>
Fri, 19 Aug 2016 13:49:31 +0000 (14:49 +0100)
committerYao Qi <yao.qi@linaro.org>
Fri, 19 Aug 2016 13:50:09 +0000 (14:50 +0100)
commit03bcd7394eefb9399f5ab97919a0463dea274c02
treee335381414a10fb5023b950ad6a3039355e47e8c
parentbbfa2517ded26c1ba9e1af37671565a1a5e6bbc6
[AArch64] Match instruction "STP with base register" in prologue

Nowadays, we only match pre-indexed STP in prologue.  Due to the change
in gcc, https://gcc.gnu.org/ml/gcc-patches/2016-07/msg01933.html, it
may generate "STP with base register" in prologue, which GDB doesn't
handle.  That is to say, previously GCC generates prologue like this,

 sub sp, sp, #490
 stp x29, x30, [sp, #-96]!
 mov x29, sp

with the gcc patch above, GCC generates prologue like like this,

 sub sp, sp, #4f0
 stp x29, x30, [sp]
 mov x29, sp

This patch is to teach GDB to recognize this instruction in prologue
analysis.

gdb:

2016-08-19  Yao Qi  <yao.qi@linaro.org>

* aarch64-tdep.c (aarch64_analyze_prologue): Handle register
based STP instruction.
gdb/ChangeLog
gdb/aarch64-tdep.c