projects / external / binutils.git / commit
? search:
summary | shortlog | log | commit | commitdiff | tree
(parent: 9494d96) | patch
RISC-V: Fix assembler for c.addi, rd can be x0
authorKito Cheng <kito.cheng@gmail.com>
Tue, 7 Mar 2017 11:56:40 +0000 (19:56 +0800)
committerPalmer Dabbelt <palmer@dabbelt.com>
Wed, 15 Mar 2017 14:47:52 +0000 (07:47 -0700)
commit03b039a518fa0f89a9900a44a8b874cc91061305
tree4d83666b8fe704570f84e15d96b5d2e07cbe9a14tree | snapshot
parent9494d9636612cd9bd22e38625fbc89147beafea7commit | diff
RISC-V: Fix assembler for c.addi, rd can be x0

opcodes/ChangeLog:

2017-03-14  Kito Cheng  <kito.cheng@gmail.com>

* riscv-opc.c (riscv_opcodes) <c.addi>: Use match_opcode.
opcodes/ChangeLog diff | blob | history
opcodes/riscv-opc.c diff | blob | history
Domain: System / Toolchain;