clk: mxs: Fix invalid 32-bit access to frac registers
authorStefan Wahren <stefan.wahren@i2se.com>
Fri, 30 Jan 2015 19:20:10 +0000 (19:20 +0000)
committerMichael Turquette <mturquette@linaro.org>
Tue, 3 Feb 2015 21:08:05 +0000 (13:08 -0800)
commit039e5970750775f102b255de9bf914e04955c6da
tree894eff0d0882ee0c4d3304c7ad8b3b8fd0cbd907
parent6793a30a0646d2cc269e66782ca30c6025c92e1f
clk: mxs: Fix invalid 32-bit access to frac registers

According to i.MX23 and i.MX28 reference manual [1],[2] the fractional
clock control register is 32-bit wide, but is separated in 4 parts.
So write instructions must not apply to more than 1 part at once.

The clk init for the i.MX28 violates this restriction and all the other
accesses on that register suggest that there isn't such a restriction.

This patch restricts the access to this register to byte instructions and
extends the comment in the init functions.

Btw the imx23 init now uses a R-M-W sequence just like imx28 init
to avoid any clock glitches.

The changes has been tested with a i.MX23 and a i.MX28 board.

[1] - http://cache.freescale.com/files/dsp/doc/ref_manual/IMX23RM.pdf
[2] - http://cache.freescale.com/files/dsp/doc/ref_manual/MCIMX28RM.pdf

Signed-off-by: Stefan Wahren <stefan.wahren@i2se.com>
Reviewed-by: Marek Vasut <marex@denx.de>
Reviewed-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Michael Turquette <mturquette@linaro.org>
drivers/clk/mxs/clk-imx23.c
drivers/clk/mxs/clk-imx28.c
drivers/clk/mxs/clk-ref.c