R600: Add 64-bit float load/store support
authorTom Stellard <thomas.stellard@amd.com>
Thu, 1 Aug 2013 15:23:42 +0000 (15:23 +0000)
committerTom Stellard <thomas.stellard@amd.com>
Thu, 1 Aug 2013 15:23:42 +0000 (15:23 +0000)
commit0344cdfe390842fd62e73a8a0cb4eb495c355076
treecbee5af8711fa2a8d8b8c137fa19b415d699a24f
parent53698938a47b6ee20542a0619908932acd07f7d5
R600: Add 64-bit float load/store support

* Added R600_Reg64 class
* Added T#Index#.XY registers definition
* Added v2i32 register reads from parameter and global space
* Added f32 and i32 elements extraction from v2f32 and v2i32
* Added v2i32 -> v2f32 conversions

Tom Stellard:
  - Mark vec2 operations as expand.  The addition of a vec2 register
    class made them all legal.

Patch by: Dmitry Cherkassov

Signed-off-by: Dmitry Cherkassov <dcherkassov@gmail.com>
llvm-svn: 187582
23 files changed:
llvm/lib/Target/R600/AMDGPUCallingConv.td
llvm/lib/Target/R600/AMDGPUISelDAGToDAG.cpp
llvm/lib/Target/R600/AMDGPUISelLowering.cpp
llvm/lib/Target/R600/R600ControlFlowFinalizer.cpp
llvm/lib/Target/R600/R600ISelLowering.cpp
llvm/lib/Target/R600/R600InstrInfo.cpp
llvm/lib/Target/R600/R600Instructions.td
llvm/lib/Target/R600/R600RegisterInfo.td
llvm/test/CodeGen/R600/64bit-kernel-args.ll
llvm/test/CodeGen/R600/build_vector.ll [new file with mode: 0644]
llvm/test/CodeGen/R600/fadd.ll
llvm/test/CodeGen/R600/fdiv.ll
llvm/test/CodeGen/R600/fmul.ll
llvm/test/CodeGen/R600/fp_to_sint.ll
llvm/test/CodeGen/R600/fp_to_uint.ll
llvm/test/CodeGen/R600/fsub.ll
llvm/test/CodeGen/R600/load.ll
llvm/test/CodeGen/R600/load.vec.ll
llvm/test/CodeGen/R600/setcc.ll
llvm/test/CodeGen/R600/sint_to_fp.ll
llvm/test/CodeGen/R600/store.ll
llvm/test/CodeGen/R600/sub.ll
llvm/test/CodeGen/R600/uint_to_fp.ll