ARM: dts: dra7-clock: Add "l3init_960m_gfclk" clock gate
authorRoger Quadros <rogerq@ti.com>
Mon, 5 May 2014 09:54:43 +0000 (12:54 +0300)
committerTony Lindgren <tony@atomide.com>
Wed, 14 May 2014 21:39:34 +0000 (14:39 -0700)
commit032d774575dfed145e4477b47579fd51d9c102b3
tree09cf7b8a4a762d950b3c3e2c4025c999238d8818
parentc65d0ad51022b2fa250a3561cc370fcbfe23beda
ARM: dts: dra7-clock: Add "l3init_960m_gfclk" clock gate

This clock gate description is missing in the older Reference manuals.
It is present on the SoC to provide 960MHz reference clock to the
internal USB PHYs.

Reference: DRA75x_DRA74x_ES1.1_NDA_TRM_vO.pdf, pg. 900,
Table 3-812. CM_COREAON_L3INIT_60M_GFCLK_CLKCTRL

Use l3init_960m_gfclk as parent of usb_otg_ss1_refclk960m and
usb_otg_ss2_refclk960m.

CC: BenoƮt Cousson <bcousson@baylibre.com>
Acked-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
arch/arm/boot/dts/dra7xx-clocks.dtsi