drm/pl111: Register the clock divider and use it.
authorEric Anholt <eric@anholt.net>
Mon, 8 May 2017 19:33:48 +0000 (12:33 -0700)
committerEric Anholt <eric@anholt.net>
Fri, 19 May 2017 18:11:35 +0000 (11:11 -0700)
commit032838f9cb4014af8a974374db9e2ce6f3aa8d3b
tree4fc8a4219ad3fdd59d8ced82cdf746f6bad34899
parent2098105ec65cb364f3d77baa446b2ad5ba6bc7b9
drm/pl111: Register the clock divider and use it.

This is required for the panel to work on bcm911360, where CLCDCLK is
the fixed 200Mhz AXI41 clock.  The rate set is still passed up to the
CLCDCLK, for platforms that have a settable rate on that one.

v2: Set SET_RATE_PARENT (caught by Linus Walleij), depend on
    COMMON_CLK.
v3: Mark the clk_ops static (caught by Stephen).

Signed-off-by: Eric Anholt <eric@anholt.net>
Link: http://patchwork.freedesktop.org/patch/msgid/20170508193348.30236-1-eric@anholt.net
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Reviewed-by: Stephen Boyd <sboyd@codeaurora.org>
drivers/gpu/drm/pl111/Kconfig
drivers/gpu/drm/pl111/pl111_display.c
drivers/gpu/drm/pl111/pl111_drm.h
drivers/gpu/drm/pl111/pl111_drv.c
include/linux/amba/clcd-regs.h