perf_counter, x86: Implement generalized cache event types, add Core2 support
authorThomas Gleixner <tglx@linutronix.de>
Mon, 8 Jun 2009 05:42:04 +0000 (07:42 +0200)
committerIngo Molnar <mingo@elte.hu>
Mon, 8 Jun 2009 09:18:26 +0000 (11:18 +0200)
commit0312af84164215a452f2a94957ebd9bce86e0204
treea0a26be68412bf928e9e8e3db112abdad581027a
parente779898aa74cd2e97216368b3f3689ceffe8aeed
perf_counter, x86: Implement generalized cache event types, add Core2 support

Fill in core2_hw_cache_event_id[] with the Core2 model specific events.

The events can be used in all the tools via the -e (--event) parameter,
for example "-e l1-misses" or -"-e l2-accesses" or "-e l2-write-misses".

Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Cc: Peter Zijlstra <a.p.zijlstra@chello.nl>
Cc: Mike Galbraith <efault@gmx.de>
Cc: Paul Mackerras <paulus@samba.org>
Cc: Arnaldo Carvalho de Melo <acme@redhat.com>
LKML-Reference: <new-submission>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
arch/x86/kernel/cpu/perf_counter.c