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(parent: 1bedb23) | patch
[X86] Match vpmullq latency to uops.info. Correct port usage for 512-bit memory form
authorCraig Topper <craig.topper@intel.com>
Tue, 3 Mar 2020 20:16:01 +0000 (12:16 -0800)
committerCraig Topper <craig.topper@intel.com>
Tue, 3 Mar 2020 20:16:03 +0000 (12:16 -0800)
commit02f03a6fd4cd64730e6229e0202404d90079b8d1
tree5f268be71c4644a530be47bcb5ce87835daa6b47tree | snapshot
parent1bedb2340774099fd3faa6610a78119a4f802955commit | diff
[X86] Match vpmullq latency to uops.info. Correct port usage for 512-bit memory form

uops.info says these should be 15 cycle instructions. Uops.info also shows the 512-bit form uses port 0 and 5 for both register and memory. We had memory using 0 and 1.

Differential Revision: https://reviews.llvm.org/D75549
llvm/lib/Target/X86/X86SchedSkylakeServer.td diff | blob | history
llvm/test/tools/llvm-mca/X86/SkylakeServer/resources-avx512dq.s diff | blob | history
llvm/test/tools/llvm-mca/X86/SkylakeServer/resources-avx512dqvl.s diff | blob | history
Domain: System / Toolchain;