MIPS: mm: c-r4k: Detect instruction cache aliases
authorMarkos Chandras <markos.chandras@imgtec.com>
Thu, 30 Jan 2014 17:21:29 +0000 (17:21 +0000)
committerRalf Baechle <ralf@linux-mips.org>
Thu, 6 Mar 2014 20:25:21 +0000 (21:25 +0100)
commit02dc6bfb080e8205aacea5c4b4dd6a9bd4c9406e
tree08224e4eb6d1b1471cc3322b626250e2d82bce7e
parent0414855fdc4a40da05221fc6062cccbc0c30f169
MIPS: mm: c-r4k: Detect instruction cache aliases

The *Aptiv cores can use the CONF7/IAR bit to detect if the core
has hardware support to remove instruction cache aliasing.

This also defines the CONF7/AR bit in order to avoid using
the '16' magic number.

Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/6499/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
arch/mips/include/asm/mipsregs.h
arch/mips/mm/c-r4k.c