drm/i915/guc/slpc: Cache platform frequency limits
authorVinay Belgaumkar <vinay.belgaumkar@intel.com>
Fri, 30 Jul 2021 20:21:16 +0000 (13:21 -0700)
committerJohn Harrison <John.C.Harrison@Intel.com>
Tue, 3 Aug 2021 23:05:38 +0000 (16:05 -0700)
commit025cb07bebfaf9e3703f902cce92b4656129a62b
tree79f421a597b17acaa622f695088c5dacb3f2ae9a
parent899a0fd73a41f3e3babedbc2e5bf73fd38a4461f
drm/i915/guc/slpc: Cache platform frequency limits

Cache rp0, rp1 and rpn platform limits into SLPC structure
for range checking while setting min/max frequencies.

Also add "soft" limits which keep track of frequency changes
made from userland. These are initially set to platform min
and max.

v2: Address review comments (Michal W)
v3: Formatting (Michal W)
v4: Add separate function to parse rp values (Michal W)
v5: Perform range checking for set min/max (Michal W)
v6: checkpatch() and rename static functions (Michal W)
v7: check ret code while setting SLPC limits (Michal W)

Signed-off-by: Vinay Belgaumkar <vinay.belgaumkar@intel.com>
Reviewed-by: Michal Wajdeczko <michal.wajdeczko@intel.com>
Signed-off-by: John Harrison <John.C.Harrison@Intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210730202119.23810-12-vinay.belgaumkar@intel.com
drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
drivers/gpu/drm/i915/gt/uc/intel_guc_slpc_types.h
drivers/gpu/drm/i915/i915_reg.h