[AArch64][SVE 19/32] Refactor address-printing code
authorRichard Sandiford <richard.sandiford@arm.com>
Wed, 21 Sep 2016 15:51:43 +0000 (16:51 +0100)
committerRichard Sandiford <richard.sandiford@arm.com>
Wed, 21 Sep 2016 15:51:43 +0000 (16:51 +0100)
commit01dbfe4c0e2b832c6b1076e8d373b162e2faa376
tree2e7c402a08b6ba05bef7fb03c6c3be5ce33a3101
parent72e9f31937f063ed6f5991a2b8c00068fa2dc8fc
[AArch64][SVE 19/32] Refactor address-printing code

SVE adds addresses in which the base or offset are vector registers.
The addresses otherwise have the same kind of form as normal AArch64
addresses, including things like SXTW with or without a shift, UXTW
with or without a shift, and LSL.

This patch therefore refactors the address-printing code so that it
can cope with both scalar and vector registers.

opcodes/
* aarch64-opc.c (get_offset_int_reg_name): New function.
(print_immediate_offset_address): Likewise.
(print_register_offset_address): Take the base and offset
registers as parameters.
(aarch64_print_operand): Update caller accordingly.  Use
print_immediate_offset_address.
opcodes/ChangeLog
opcodes/aarch64-opc.c