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(parent: 9b914aa) | patch
[SVE][InstCombine] Support more cases where ld1/st1 can be lowered to load/store...
authorPaul Walker <paul.walker@arm.com>
Fri, 3 Dec 2021 14:36:54 +0000 (14:36 +0000)
committerPaul Walker <paul.walker@arm.com>
Wed, 8 Dec 2021 11:01:33 +0000 (11:01 +0000)
commit01bc67e449a91d05d20d36630c9fb99573339ec4
tree8965a1f87c3ec012cba1c81b8c02f311b2864a3atree | snapshot
parent9b914aacbd5414e48fa2a58e0082e7b69c783278commit | diff
[SVE][InstCombine] Support more cases where ld1/st1 can be lowered to load/store instructions.

This patch extends the "is all active predicate" check to cover
cases where the predicate is casted but in a way that doesn't
change its "all active" status.

Differential Revision: https://reviews.llvm.org/D115047
llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp diff | blob | history
llvm/test/Transforms/InstCombine/AArch64/sve-intrinsic-loadstore.ll diff | blob | history
Domain: System / Toolchain;