projects / platform / upstream / llvm.git / commit
? search:
summary | shortlog | log | commit | commitdiff | tree
(parent: 9c8ebeb) | patch
[Hexagon] Marking several instructions as isCodeGenOnly=0 and adding direct disassemb...
authorColin LeMahieu <colinl@codeaurora.org>
Fri, 5 Dec 2014 17:27:39 +0000 (17:27 +0000)
committerColin LeMahieu <colinl@codeaurora.org>
Fri, 5 Dec 2014 17:27:39 +0000 (17:27 +0000)
commit01785bb063f245cc43e1c537301a8b4a6b7bf19d
treed3053a88be0c726f93491811d8ee833352fb318ctree | snapshot
parent9c8ebeb03d53ecc77281786d14cacd552dee1d6dcommit | diff
[Hexagon] Marking several instructions as isCodeGenOnly=0 and adding direct disassembly tests for many instructions.

llvm-svn: 223482
llvm/lib/Target/Hexagon/HexagonInstrInfo.td diff | blob | history
llvm/test/MC/Disassembler/Hexagon/alu32_alu.txt diff | blob | history
llvm/test/MC/Disassembler/Hexagon/alu32_perm.txt [new file with mode: 0644] blob
llvm/test/MC/Disassembler/Hexagon/alu32_pred.txt [new file with mode: 0644] blob
Domain: System / Toolchain;