mmc: sunxi: Fix DDR MMC timings for A80
authorChen-Yu Tsai <wens@csie.org>
Sun, 29 May 2016 07:04:43 +0000 (15:04 +0800)
committerUlf Hansson <ulf.hansson@linaro.org>
Thu, 2 Jun 2016 08:40:02 +0000 (10:40 +0200)
commit0175249efa9310eed79650209600a75ace656bc9
treed82ee91f941393a1e182efa080ce822685def7ec
parentf741494363c6c90e6744117d2771bbdf0fb3c455
mmc: sunxi: Fix DDR MMC timings for A80

The MMC clock timings were incorrectly calculated, when the conversion
from delay value to delay phase was done.

The 50M DDR and 50M DDR 8bit timings are off, and make eMMC DDR
unusable. Unfortunately it seems different controllers on the same SoC
have different timings. The new settings are taken from mmc2, which is
commonly used with eMMC.

The settings for the slower timing modes seem to work despite being
wrong, so leave them be.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
drivers/mmc/host/sunxi-mmc.c