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(parent: 3285f1b) | patch
Fix PR 24724 - The implicit register verifier shouldn't assume certain operand
authorAlex Lorenz <arphaman@gmail.com>
Thu, 10 Sep 2015 14:04:34 +0000 (14:04 +0000)
committerAlex Lorenz <arphaman@gmail.com>
Thu, 10 Sep 2015 14:04:34 +0000 (14:04 +0000)
commit0153e59935cb14302e01e5546afc00a2575ecbf8
treeaf334c15d80c3b39bf1ca1868fa1bfd90c349f08tree | snapshot
parent3285f1b850b736f507772b64b1a16e55fe2c1afccommit | diff
Fix PR 24724 - The implicit register verifier shouldn't assume certain operand
order.

The implicit register verifier in the MIR parser should only check if the
instruction's default implicit operands are present in the instruction. It
should not check the order in which they occur.

llvm-svn: 247283
llvm/lib/CodeGen/MIRParser/MIParser.cpp diff | blob | history
llvm/test/CodeGen/MIR/PowerPC/lit.local.cfg [new file with mode: 0644] blob
llvm/test/CodeGen/MIR/PowerPC/unordered-implicit-registers.mir [new file with mode: 0644] blob
llvm/test/CodeGen/MIR/X86/expected-different-implicit-operand.mir diff | blob | history
llvm/test/CodeGen/MIR/X86/expected-different-implicit-register-flag.mir diff | blob | history
Domain: System / Toolchain;