drm/i915/tgl: Fixing up list of PG3 power domains.
authorAnshuman Gupta <anshuman.gupta@intel.com>
Sun, 11 Aug 2019 10:02:32 +0000 (15:32 +0530)
committerImre Deak <imre.deak@intel.com>
Mon, 12 Aug 2019 09:04:24 +0000 (12:04 +0300)
commit015341da9888b58fbdeafd369c43f7a95fe4e763
tree0e9394e209b63501d27a30fe9c4cae4cde87659e
parent2e04dbceed682a97c44cf50fd73c7cfc79e208ea
drm/i915/tgl: Fixing up list of PG3 power domains.

The DDI-IO power wells (PWR_WELL_CTL_DDI) are backing
the IO/PHY functionality, which doesn't need the PG3
power power well. Accordingly fixing up the list of
PG3 power domains.

Cc: Imre Deak <imre.deak@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Imre Deak <imre.deak@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190811100232.27964-1-anshuman.gupta@intel.com
drivers/gpu/drm/i915/display/intel_display_power.c