KVM: MIPS/T&E: Expose CP0_EntryLo0/1 registers
authorJames Hogan <james.hogan@imgtec.com>
Wed, 7 Dec 2016 17:16:37 +0000 (17:16 +0000)
committerJames Hogan <james.hogan@imgtec.com>
Fri, 3 Feb 2017 15:21:32 +0000 (15:21 +0000)
commit013044cc65f8661c5fa2b59da5e134b3453d975d
tree801ef5a0bad1220d2d1b6fc271e11dfaf5e7d9bd
parentbe67a0be94b65746dee63af5c184c78d00a707f6
KVM: MIPS/T&E: Expose CP0_EntryLo0/1 registers

Expose the CP0_EntryLo0 and CP0_EntryLo1 registers through the KVM
register access API. This is fairly straightforward for trap & emulate
since we don't support the RI and XI bits. For the sake of future
proofing (particularly for VZ) it is explicitly specified that the API
always exposes the 64-bit version of these registers (i.e. with the RI
and XI bits in bit positions 63 and 62 respectively), and they are
implemented in trap_emul.c rather than mips.c to allow them to be
implemented differently for VZ.

Signed-off-by: James Hogan <james.hogan@imgtec.com>
Cc: Paolo Bonzini <pbonzini@redhat.com>
Cc: "Radim Krčmář" <rkrcmar@redhat.com>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: linux-mips@linux-mips.org
Cc: kvm@vger.kernel.org
Documentation/virtual/kvm/api.txt
arch/mips/include/asm/kvm_host.h
arch/mips/kvm/trap_emul.c