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author	Yaxun Liu <Yaxun.Liu@amd.com>
	Tue, 13 Feb 2018 18:00:25 +0000 (18:00 +0000)
committer	Yaxun Liu <Yaxun.Liu@amd.com>
	Tue, 13 Feb 2018 18:00:25 +0000 (18:00 +0000)
commit	0124b5484cdd254571e8b17b0ac510aec5edf1a5
tree	cab176450e673f3e1d9caedcd290edd1884660f4	tree \| snapshot
parent	18c0247852f717b3d72cbf0f8635e3108ff10613	commit \| diff

[AMDGPU] Change constant addr space to 4

Differential Revision: https://reviews.llvm.org/D43170

llvm-svn: 325030

90 files changed:

llvm/docs/AMDGPUUsage.rst		diff \| blob \| history
llvm/include/llvm/IR/IntrinsicsAMDGPU.td		diff \| blob \| history
llvm/lib/Target/AMDGPU/AMDGPU.h		diff \| blob \| history
llvm/lib/Target/AMDGPU/AMDGPUAliasAnalysis.cpp		diff \| blob \| history
llvm/lib/Target/AMDGPU/AMDGPUCallLowering.cpp		diff \| blob \| history
llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp		diff \| blob \| history
llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp		diff \| blob \| history
llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-smrd.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-amdgpu_vs.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/smrd.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/add.v2i16.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/addrspacecast.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/amdgpu.private-memory.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/annotate-kernel-features-hsa-call.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/annotate-kernel-features-hsa.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/branch-relaxation.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/call-argument-types.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/callee-special-input-sgprs.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/cgp-addressing-modes-flat.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/cgp-addressing-modes.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/early-if-convert-cost.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/early-if-convert.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/extract_vector_elt-f16.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/extract_vector_elt-i16.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/fence-barrier.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/function-returns.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/global-constant.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/gv-const-addrspace.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/hsa-func-align.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/hsa-func.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/hsa-metadata-from-llvm-ir-full.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/image-schedule.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/insert_vector_elt.v2i16.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/invariant-load-no-alias-store.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/llvm.SI.load.dword.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.dispatch.ptr.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.implicit.buffer.ptr.hsa.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.implicit.buffer.ptr.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.implicitarg.ptr.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.kernarg.segment.ptr.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.queue.ptr.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/llvm.memcpy.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/load-constant-f64.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/load-constant-i1.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/load-constant-i16.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/load-constant-i32.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/load-constant-i64.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/load-constant-i8.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/load-hi16.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/load-lo16.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/mad24-get-global-id.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/missing-store.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/mubuf-shader-vgpr.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/mubuf.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/multi-divergent-exit-region.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/no-initializer-constant-addrspace.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/no-shrink-extloads.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/nullptr.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/pack.v2f16.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/pack.v2i16.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/r600-constant-array-fixup.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/readcyclecounter.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/ret.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/salu-to-valu.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/sched-crash-dbg-value.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/sext-in-reg.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/sgpr-copy.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/si-lod-bias.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/si-scheduler.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/si-sgpr-spill.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/si-triv-disjoint-mem-access.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/smrd-vccz-bug.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/smrd.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/spill-m0.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/split-smrd.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/store-global.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/store-private.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/sub.v2i16.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/target-cpu.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/unaligned-load-store.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/uniform-crash.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/vertex-fetch-encoding.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/vgpr-spill-emergency-stack-slot.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/wait.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/waitcnt-looptest.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/widen_extending_scalar_loads.ll		diff \| blob \| history
llvm/test/Transforms/SeparateConstOffsetFromGEP/AMDGPU/split-gep-and-gvn-addrspace-addressing-modes.ll		diff \| blob \| history

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