Revert "[RISCV] Use zexti32/sexti32 in srliw/sraiw isel patterns to improve usage...
authorCraig Topper <craig.topper@sifive.com>
Sun, 27 Jun 2021 17:32:48 +0000 (10:32 -0700)
committerCraig Topper <craig.topper@sifive.com>
Sun, 27 Jun 2021 17:33:43 +0000 (10:33 -0700)
commit010f0f000f1f6a5461ac96ad075030a2fd7bb720
treecf642d624a4680a8645ab90a9ec61c8f3e306c48
parentf00941e061f39646b05fcab93f892fc793845da1
Revert "[RISCV] Use zexti32/sexti32 in srliw/sraiw isel patterns to improve usage of those instructions."

I thought this might help with another optimization I was
thinking about, but I don't think it will. So it just wastes
compile time calling computeKnownBits for no benefit.

This reverts commit 81b2f95971edd47a0057ac4a77b674d7ea620c01.
14 files changed:
llvm/lib/Target/RISCV/RISCVInstrInfo.td
llvm/test/CodeGen/RISCV/alu8.ll
llvm/test/CodeGen/RISCV/bswap-ctlz-cttz-ctpop.ll
llvm/test/CodeGen/RISCV/copysign-casts.ll
llvm/test/CodeGen/RISCV/div.ll
llvm/test/CodeGen/RISCV/rv64i-exhaustive-w-insts.ll
llvm/test/CodeGen/RISCV/rv64zbb-zbp.ll
llvm/test/CodeGen/RISCV/rv64zbb.ll
llvm/test/CodeGen/RISCV/rv64zbp.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctlz.ll
llvm/test/CodeGen/RISCV/urem-lkk.ll
llvm/test/CodeGen/RISCV/urem-seteq-illegal-types.ll
llvm/test/CodeGen/RISCV/urem-vector-lkk.ll
llvm/test/CodeGen/RISCV/vec3-setcc-crash.ll