review.tizen.org Git - platform/kernel/linux-starfive.git/commit

author	Mauro Rossi <issor.oruam@gmail.com>
	Sun, 12 Aug 2018 19:43:02 +0000 (21:43 +0200)
committer	Alex Deucher <alexander.deucher@amd.com>
	Mon, 27 Aug 2018 16:10:19 +0000 (11:10 -0500)
commit	00ecc6e6d4eeba9681ec91f9601a9ed1a68a9e7f
tree	dd68479a6bf7022b6084b8377e7bae237d3f9424	tree \| snapshot
parent	bcd47f60ab65c780eef44cc09c0e264453dd455e	commit \| diff

drm/amdgpu: enable ABGR and XBGR formats (v2)

Add support for DRM_FORMAT_{A,X}BGR8888 in amdgpu with amd dc disabled

(v2) Crossbar registers are defined and used to swap red and blue channels,
     keeping the existing coding style in each of the dce modules.
     After setting crossbar bits in fb_swap, use bitwise OR for big endian
     where required in DCE6 and DCE8 which do not rely on REG_SET_FIELD()

Signed-off-by: Mauro Rossi <issor.oruam@gmail.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

drivers/gpu/drm/amd/amdgpu/dce_v10_0.c		diff \| blob \| history
drivers/gpu/drm/amd/amdgpu/dce_v11_0.c		diff \| blob \| history
drivers/gpu/drm/amd/amdgpu/dce_v6_0.c		diff \| blob \| history
drivers/gpu/drm/amd/amdgpu/dce_v8_0.c		diff \| blob \| history
drivers/gpu/drm/amd/amdgpu/si_enums.h		diff \| blob \| history
drivers/gpu/drm/amd/amdgpu/sid.h		diff \| blob \| history