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(parent: 60cc43f) | patch
clk: mvebu: use correct bit for 98DX3236 NAND
authorChris Packham <chris.packham@alliedtelesis.co.nz>
Thu, 24 May 2018 05:23:41 +0000 (17:23 +1200)
committerStephen Boyd <sboyd@kernel.org>
Fri, 1 Jun 2018 19:46:33 +0000 (12:46 -0700)
commit00c5a926af12a9f0236928dab3dc9faf621406a1
tree50771e7c9a880b3c5c86574d173487e3d2a5e7detree | snapshot
parent60cc43fc888428bb2f18f08997432d426a243338commit | diff
clk: mvebu: use correct bit for 98DX3236 NAND

The correct fieldbit value for the NAND PLL reload trigger is 27.

Fixes: commit e120c17a70e5 ("clk: mvebu: support for 98DX3236 SoC")
Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
drivers/clk/mvebu/clk-corediv.c diff | blob | history
Domain: System / Kernel;