iio: dac: ad5504: Fix alignment for DMA safety
authorJonathan Cameron <Jonathan.Cameron@huawei.com>
Sun, 8 May 2022 17:56:27 +0000 (18:56 +0100)
committerJonathan Cameron <Jonathan.Cameron@huawei.com>
Tue, 14 Jun 2022 10:53:16 +0000 (11:53 +0100)
commit00b9737caa5aaed5cf45a7c7498edf5957efa3b2
tree2fdaa13677babe561881a1ae7a88c29fe5078b02
parent678d536bb454e3bbedcaa68208550ac9dc1cc066
iio: dac: ad5504: Fix alignment for DMA safety

____cacheline_aligned is an insufficient guarantee for non-coherent DMA
on platforms with 128 byte cachelines above L1.  Switch to the updated
IIO_DMA_MINALIGN definition.

Fixes: 0dbe59c7a788 ("iio:ad5504: Do not store transfer buffers on the stack")
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Cc: Lars-Peter Clausen <lars@metafoo.de>
Acked-by: Nuno Sá <nuno.sa@analog.com>
Link: https://lore.kernel.org/r/20220508175712.647246-48-jic23@kernel.org
drivers/iio/dac/ad5504.c