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(parent: 243c288) | patch
Minor SPARC T4 and M7 fixes and additions.
authorSheldon Lobo <sheldon.lobo@oracle.com>
Thu, 18 May 2017 09:34:26 +0000 (09:34 +0000)
committerSheldon Lobo <smlobo@gcc.gnu.org>
Thu, 18 May 2017 09:34:26 +0000 (09:34 +0000)
commit00a84d0eddec8e671f48e209fffac7c97e6bc4bf
tree3073cf46a77e5e964b3e0c4db99086e8a4fe43b8tree | snapshot
parent243c288370fe51ba55c3a9ee61eb2a1a62cb1279commit | diff
Minor SPARC T4 and M7 fixes and additions.

* config/sparc/sparc.c (sparc_option_override): Set function
alignment for -mcpu=niagara7 to 64 to match the I$ line.
* config/sparc/sparc.h (BRANCH_COST): Set the SPARC M7 branch
latency to 1.
* config/sparc/sparc.h (BRANCH_COST): Set the SPARC T4 branch
latency to 2.
* config/sparc/sol2.h: Fix a ASM_CPU32_DEFAULT_SPEC typo.
* gcc.target/sparc/niagara7-align.c: New test.

From-SVN: r248184
gcc/ChangeLog diff | blob | history
gcc/config/sparc/sol2.h diff | blob | history
gcc/config/sparc/sparc.c diff | blob | history
gcc/config/sparc/sparc.h diff | blob | history
gcc/testsuite/ChangeLog diff | blob | history
gcc/testsuite/gcc.target/sparc/niagara7-align.c [new file with mode: 0644] blob
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