RISC-V: Add PCIe I/O BAR memory mapping
authorYash Shah <yash.shah@sifive.com>
Fri, 25 Oct 2019 08:30:03 +0000 (08:30 +0000)
committerPaul Walmsley <paul.walmsley@sifive.com>
Mon, 28 Oct 2019 17:43:32 +0000 (10:43 -0700)
commit00a5bf3a8ca30d19f24219fc3cfb74f4eab3600d
treeca4482fe65348fc5321ed6093a9f5352fe70bb5b
parentf307307992bf63e609fe5395953048e81c9ebc54
RISC-V: Add PCIe I/O BAR memory mapping

For legacy I/O BARs (non-MMIO BARs) to work correctly on RISC-V Linux,
we need to establish a reserved memory region for them, so that drivers
that wish to use the legacy I/O BARs can issue reads and writes against
a memory region that is mapped to the host PCIe controller's I/O BAR
mapping.

Signed-off-by: Yash Shah <yash.shah@sifive.com>
Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com>
arch/riscv/include/asm/io.h
arch/riscv/include/asm/pgtable.h