[X86] Split WriteIMul into 8/16/32/64 implementations (PR36931)
authorSimon Pilgrim <llvm-dev@redking.me.uk>
Mon, 24 Sep 2018 15:21:57 +0000 (15:21 +0000)
committerSimon Pilgrim <llvm-dev@redking.me.uk>
Mon, 24 Sep 2018 15:21:57 +0000 (15:21 +0000)
commit00865a48d18b49f2605a70aeb48b015c1f6f5708
treea7d48b2c4878ed38f9bf1530bbfe69c98a39f578
parentab7f9b170d854b8d5be55a94f48ad67727b4d0bc
[X86] Split WriteIMul into 8/16/32/64 implementations (PR36931)

Split WriteIMul by size and also by IMUL multiply-by-imm and multiply-by-reg cases.

This removes all the scheduler overrides for gpr multiplies and stops WriteMULH being ignored for BMI2 MULX instructions.

llvm-svn: 342892
17 files changed:
llvm/lib/Target/X86/X86InstrArithmetic.td
llvm/lib/Target/X86/X86SchedBroadwell.td
llvm/lib/Target/X86/X86SchedHaswell.td
llvm/lib/Target/X86/X86SchedSandyBridge.td
llvm/lib/Target/X86/X86SchedSkylakeClient.td
llvm/lib/Target/X86/X86SchedSkylakeServer.td
llvm/lib/Target/X86/X86Schedule.td
llvm/lib/Target/X86/X86ScheduleAtom.td
llvm/lib/Target/X86/X86ScheduleBtVer2.td
llvm/lib/Target/X86/X86ScheduleSLM.td
llvm/lib/Target/X86/X86ScheduleZnver1.td
llvm/test/CodeGen/X86/bmi2-schedule.ll
llvm/test/tools/llvm-mca/X86/Broadwell/resources-bmi2.s
llvm/test/tools/llvm-mca/X86/Generic/resources-bmi2.s
llvm/test/tools/llvm-mca/X86/Haswell/resources-bmi2.s
llvm/test/tools/llvm-mca/X86/SkylakeClient/resources-bmi2.s
llvm/test/tools/llvm-mca/X86/SkylakeServer/resources-bmi2.s