[RISCV] Add support for Zihintpause extention
authorShao-Ce SUN <shaoce@nj.iscas.ac.cn>
Thu, 20 Jan 2022 15:49:55 +0000 (23:49 +0800)
committerShao-Ce SUN <shaoce@nj.iscas.ac.cn>
Thu, 3 Feb 2022 12:55:47 +0000 (20:55 +0800)
commit005fd8aa702edbc532763038365575da96e5787d
treeda5ccf1e8c8801d18f64b9bc8968d629a38ba967
parent6f53960d6416b97e4c750b132b5662b80df12ee9
[RISCV] Add support for Zihintpause extention

Add support for the 'pause' hint instruction as an alias for
'fence w, 0'. To do this allow the 'fence' operands pred and succ
to be set to 0 (the empty set). This will also allow future hints
to be encoded as 'fence 0, <x>' and 'fence <x>, 0'.

This patch revised from @mundaym's D93019.

Reviewed By: asb

Differential Revision: https://reviews.llvm.org/D117789
llvm/lib/Support/RISCVISAInfo.cpp
llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp
llvm/lib/Target/RISCV/RISCV.td
llvm/lib/Target/RISCV/RISCVInstrInfo.td
llvm/lib/Target/RISCV/RISCVSubtarget.h
llvm/test/CodeGen/RISCV/attributes.ll
llvm/test/MC/Disassembler/RISCV/unknown-fence-field.txt [deleted file]
llvm/test/MC/RISCV/rv32i-invalid.s
llvm/test/MC/RISCV/rv32zihintpause-valid.s [new file with mode: 0644]
llvm/test/MC/RISCV/rvzihintpause-aliases-valid.s [new file with mode: 0644]