RISC-V: Fix bugs for refine vsetvl a5, zero into vsetvl zero, zero incorrectly

RISC-V: Fix bugs for refine vsetvl a5, zero into vsetvl zero, zero incorrectly

Currently we support this optimization:

bb 0:
 vsetvli a5,zero,e32,mf2
bb 1:
 vsetvli a5,zero,e64,m1 --> vsetvli zero,zero,e64,m1

According RVV ISA, we can do this optimization only if both RATIO and AVL are equal.
However, current VSETVL PASS missed the check of AVL. This patch add this condition
check to fix bugs.

gcc/ChangeLog:

	* config/riscv/riscv-vsetvl.cc (vector_infos_manager::all_same_avl_p): New function.
	(pass_vsetvl::can_refine_vsetvl_p): Add AVL check.
	(pass_vsetvl::commit_vsetvls): Ditto.
	* config/riscv/riscv-vsetvl.h: New function declaration.