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(parent: 2d7a578) | patch
riscv: dts: jh7110: Add PLL clock controller node
authorXingyu Wu <xingyu.wu@starfivetech.com>
Fri, 7 Jul 2023 10:50:08 +0000 (18:50 +0800)
committerLeo Yu-Chi Liang <ycliang@andestech.com>
Mon, 24 Jul 2023 05:21:01 +0000 (13:21 +0800)
commit005f9627d02e8ecab3c58c77889060e72f7fa25d
treeb63fe4485552248aba0081de015f913ddd4c1243tree | snapshot
parent2d7a5787915716040ec381d1cf5064a3401ed12acommit | diff
riscv: dts: jh7110: Add PLL clock controller node

Add child node about PLL clock controller in sys_syscon node.

Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
Reviewed-by: Torsten Duwe <duwe@suse.de>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
arch/riscv/dts/jh7110.dtsi diff | blob | history
Domain: System / Kernel;