drm/i915: Force common lane on for the PPS kick on CHV
authorVille Syrjälä <ville.syrjala@linux.intel.com>
Fri, 10 Jul 2015 07:56:24 +0000 (10:56 +0300)
committerDaniel Vetter <daniel.vetter@ffwll.ch>
Wed, 26 Aug 2015 12:37:13 +0000 (14:37 +0200)
commit0047eedc48869f8c7797dd10f0cf976ac34c1d33
treecdb5159be00ba3a1cc1a49161a57173ef60075c1
parentb0b3384612bd4ce608c5d95626149311bb43f121
drm/i915: Force common lane on for the PPS kick on CHV

With DPIO powergating active the DPLL can't be accessed unless
something else is keeping the common lane in the channel on.
That means the PPS kick procedure could fail to enable the PLL.

Power up some data lanes to force the common lane to power up
so that the PLL can be enabled temporarily.

v2: Avoid gcc uninitilized variable warning

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Deepak S <deepak.s@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
drivers/gpu/drm/i915/intel_dp.c