RISC-V: Optimize masking with two clear bits not a SMALL_OPERAND
authorPhilipp Tomsich <philipp.tomsich@vrull.eu>
Thu, 13 Oct 2022 08:55:41 +0000 (10:55 +0200)
committerPhilipp Tomsich <philipp.tomsich@vrull.eu>
Thu, 17 Nov 2022 15:27:17 +0000 (16:27 +0100)
commit0045d254c010bf5eac55903780c67f725192cfb3
tree67addffd02a3858cd110e2527eafebe9484320b3
parent1957bedf29a1b2cc231972aba680fe80199d5498
RISC-V: Optimize masking with two clear bits not a SMALL_OPERAND

Add a split for cases where we can use two bclri (or one bclri and an
andi) to clear two bits.

gcc/ChangeLog:

* config/riscv/bitmanip.md (*bclri<mode>_nottwobits): New pattern.
(*bclridisi_nottwobits): New pattern, handling the sign-bit.
* config/riscv/predicates.md (const_nottwobits_operand):
New predicate.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/zbs-bclri.c: New test.
gcc/config/riscv/bitmanip.md
gcc/config/riscv/predicates.md
gcc/testsuite/gcc.target/riscv/zbs-bclri.c [new file with mode: 0644]