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author	Hsiangkai Wang <hsiangkai@google.com>
	Thu, 22 Dec 2022 07:07:37 +0000 (07:07 +0000)
committer	Hsiangkai Wang <hsiangkai@google.com>
	Thu, 29 Dec 2022 11:43:40 +0000 (11:43 +0000)
commit	002005e6740e6de8f748ed234db08625cc533195
tree	3755711e6c36eba25d9d7cf597a71f7b64541a92	tree \| snapshot
parent	947d529e4194e0567cfbbea99127066f76c87269	commit \| diff

[RISCV] Add integer scalar instructions to isAssociativeAndCommutative

Inspired by D138107.

We can add ADD, AND, OR, XOR, MUL, MIN[U]/MAX[U] to isAssociativeAndCommutative
to increase instruction-level parallelism by the existing MachineCombiner pass.

Differential Revision: https://reviews.llvm.org/D140530

47 files changed:

llvm/lib/Target/RISCV/RISCVInstrInfo.cpp		diff \| blob \| history
llvm/test/CodeGen/RISCV/addc-adde-sube-subc.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/addcarry.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/addimm-mulimm.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/alu64.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/bswap-bitreverse.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/calling-conv-ilp32-ilp32f-common.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/calling-conv-ilp32-ilp32f-ilp32d-common.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/calling-conv-lp64-lp64f-lp64d-common.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/compress.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/copysign-casts.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/div-by-constant.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/div-pow2.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/div.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/fpclamptosat.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/fpclamptosat_vec.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/iabs.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/machine-combiner.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/mul.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/neg-abs.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/rv32zbb.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/rv64zbb.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-elen.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-unaligned.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/sadd_sat.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/sadd_sat_plus.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/select-binop-identity.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/shadowcallstack.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/split-udiv-by-constant.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/srem-lkk.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/srem-seteq-illegal-types.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/srem-vector-lkk.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/ssub_sat.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/ssub_sat_plus.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/uadd_sat.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/uadd_sat_plus.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/umulo-128-legalisation-lowering.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/unaligned-load-store.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/urem-lkk.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/urem-seteq-illegal-types.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/urem-vector-lkk.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/usub_sat.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/usub_sat_plus.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/vararg.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/wide-scalar-shift-by-byte-multiple-legalization.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/wide-scalar-shift-legalization.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/xaluo.ll		diff \| blob \| history

Domain: System / Toolchain;

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