X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=src%2Fintel%2Fcompiler%2Fbrw_fs.cpp;h=e6a603a9048ba65d19d502c1f28f61998fc418f2;hb=354363cc89185c215b121218f03f9e24bc61fa9d;hp=aa01a2241ce029f36edac8b6433eb73d161cfd15;hpb=10bb376e09b1e2d328980446bfc5a227f9821fbd;p=platform%2Fupstream%2Fmesa.git

diff --git a/src/intel/compiler/brw_fs.cpp b/src/intel/compiler/brw_fs.cpp
index aa01a22..e6a603a 100644
--- a/src/intel/compiler/brw_fs.cpp
+++ b/src/intel/compiler/brw_fs.cpp
@@ -7599,7 +7599,17 @@ computed_depth_mode(const nir_shader *shader)
       case FRAG_DEPTH_LAYOUT_LESS:
          return BRW_PSCDEPTH_ON_LE;
       case FRAG_DEPTH_LAYOUT_UNCHANGED:
-         return BRW_PSCDEPTH_OFF;
+         /* We initially set this to OFF, but having the shader write the
+          * depth means we allocate register space in the SEND message. The
+          * difference between the SEND register count and the OFF state
+          * programming makes the HW hang.
+          *
+          * Removing the depth writes also leads to test failures. So use
+          * LesserThanOrEqual, which fits writing the same value
+          * (unchanged/equal).
+          *
+          */
+         return BRW_PSCDEPTH_ON_LE;
       }
    }
    return BRW_PSCDEPTH_OFF;