X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=src%2Fi965_post_processing.c;h=a82c7968591b8a6a2dda2eeada22cc6c503924d6;hb=d2213b511ec8f9902635482e251053e4a95b9668;hp=012ba2510d7dba663383023a29950aa64da4f568;hpb=f59eff566e2ad082c113b87163abca903e4d3f1d;p=profile%2Fivi%2Fvaapi-intel-driver.git diff --git a/src/i965_post_processing.c b/src/i965_post_processing.c old mode 100644 new mode 100755 index 012ba25..a82c796 --- a/src/i965_post_processing.c +++ b/src/i965_post_processing.c @@ -55,6 +55,10 @@ #define SURFACE_STATE_OFFSET(index) (SURFACE_STATE_PADDED_SIZE * index) #define BINDING_TABLE_OFFSET SURFACE_STATE_OFFSET(MAX_PP_SURFACES) +#define GPU_ASM_BLOCK_WIDTH 16 +#define GPU_ASM_BLOCK_HEIGHT 8 +#define GPU_ASM_X_OFFSET_ALIGNMENT 4 + static const uint32_t pp_null_gen5[][4] = { #include "shaders/post_processing/gen5_6/null.g4b.gen5" }; @@ -91,24 +95,54 @@ static const uint32_t pp_nv12_dn_gen5[][4] = { #include "shaders/post_processing/gen5_6/nv12_dn_nv12.g4b.gen5" }; +static const uint32_t pp_nv12_load_save_pa_gen5[][4] = { +#include "shaders/post_processing/gen5_6/nv12_load_save_pa.g4b.gen5" +}; + +static const uint32_t pp_pl3_load_save_pa_gen5[][4] = { +#include "shaders/post_processing/gen5_6/pl3_load_save_pa.g4b.gen5" +}; + +static const uint32_t pp_pa_load_save_nv12_gen5[][4] = { +#include "shaders/post_processing/gen5_6/pa_load_save_nv12.g4b.gen5" +}; + +static const uint32_t pp_pa_load_save_pl3_gen5[][4] = { +#include "shaders/post_processing/gen5_6/pa_load_save_pl3.g4b.gen5" +}; + +static const uint32_t pp_rgbx_load_save_nv12_gen5[][4] = { +#include "shaders/post_processing/gen5_6/rgbx_load_save_nv12.g4b.gen5" +}; + +static const uint32_t pp_nv12_load_save_rgbx_gen5[][4] = { +#include "shaders/post_processing/gen5_6/nv12_load_save_rgbx.g4b.gen5" +}; + static VAStatus pp_null_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context, const struct i965_surface *src_surface, const VARectangle *src_rect, struct i965_surface *dst_surface, const VARectangle *dst_rect, void *filter_param); -static VAStatus pp_nv12_avs_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context, - const struct i965_surface *src_surface, - const VARectangle *src_rect, - struct i965_surface *dst_surface, - const VARectangle *dst_rect, - void *filter_param); +static VAStatus pp_nv12_avs_initialize_nlas(VADriverContextP ctx, struct i965_post_processing_context *pp_context, + const struct i965_surface *src_surface, + const VARectangle *src_rect, + struct i965_surface *dst_surface, + const VARectangle *dst_rect, + void *filter_param); static VAStatus pp_nv12_scaling_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context, const struct i965_surface *src_surface, const VARectangle *src_rect, struct i965_surface *dst_surface, const VARectangle *dst_rect, void *filter_param); +static VAStatus gen6_nv12_scaling_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context, + const struct i965_surface *src_surface, + const VARectangle *src_rect, + struct i965_surface *dst_surface, + const VARectangle *dst_rect, + void *filter_param); static VAStatus pp_plx_load_save_plx_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context, const struct i965_surface *src_surface, const VARectangle *src_rect, @@ -210,7 +244,7 @@ static struct pp_module pp_modules_gen5[] = { NULL, }, - pp_nv12_avs_initialize, + pp_nv12_avs_initialize_nlas, }, { @@ -236,6 +270,79 @@ static struct pp_module pp_modules_gen5[] = { pp_nv12_dn_initialize, }, + + { + { + "NV12_PA module", + PP_NV12_LOAD_SAVE_PA, + pp_nv12_load_save_pa_gen5, + sizeof(pp_nv12_load_save_pa_gen5), + NULL, + }, + + pp_plx_load_save_plx_initialize, + }, + + { + { + "PL3_PA module", + PP_PL3_LOAD_SAVE_PA, + pp_pl3_load_save_pa_gen5, + sizeof(pp_pl3_load_save_pa_gen5), + NULL, + }, + + pp_plx_load_save_plx_initialize, + }, + + { + { + "PA_NV12 module", + PP_PA_LOAD_SAVE_NV12, + pp_pa_load_save_nv12_gen5, + sizeof(pp_pa_load_save_nv12_gen5), + NULL, + }, + + pp_plx_load_save_plx_initialize, + }, + + { + { + "PA_PL3 module", + PP_PA_LOAD_SAVE_PL3, + pp_pa_load_save_pl3_gen5, + sizeof(pp_pa_load_save_pl3_gen5), + NULL, + }, + + pp_plx_load_save_plx_initialize, + }, + + { + { + "RGBX_NV12 module", + PP_RGBX_LOAD_SAVE_NV12, + pp_rgbx_load_save_nv12_gen5, + sizeof(pp_rgbx_load_save_nv12_gen5), + NULL, + }, + + pp_plx_load_save_plx_initialize, + }, + + { + { + "NV12_RGBX module", + PP_NV12_LOAD_SAVE_RGBX, + pp_nv12_load_save_rgbx_gen5, + sizeof(pp_nv12_load_save_rgbx_gen5), + NULL, + }, + + pp_plx_load_save_plx_initialize, + }, + }; static const uint32_t pp_null_gen6[][4] = { @@ -259,7 +366,7 @@ static const uint32_t pp_pl3_load_save_pl3_gen6[][4] = { }; static const uint32_t pp_nv12_scaling_gen6[][4] = { -#include "shaders/post_processing/gen5_6/nv12_scaling_nv12.g6b" +#include "shaders/post_processing/gen5_6/nv12_avs_nv12.g6b" }; static const uint32_t pp_nv12_avs_gen6[][4] = { @@ -274,6 +381,30 @@ static const uint32_t pp_nv12_dn_gen6[][4] = { #include "shaders/post_processing/gen5_6/nv12_dn_nv12.g6b" }; +static const uint32_t pp_nv12_load_save_pa_gen6[][4] = { +#include "shaders/post_processing/gen5_6/nv12_load_save_pa.g6b" +}; + +static const uint32_t pp_pl3_load_save_pa_gen6[][4] = { +#include "shaders/post_processing/gen5_6/pl3_load_save_pa.g6b" +}; + +static const uint32_t pp_pa_load_save_nv12_gen6[][4] = { +#include "shaders/post_processing/gen5_6/pa_load_save_nv12.g6b" +}; + +static const uint32_t pp_pa_load_save_pl3_gen6[][4] = { +#include "shaders/post_processing/gen5_6/pa_load_save_pl3.g6b" +}; + +static const uint32_t pp_rgbx_load_save_nv12_gen6[][4] = { +#include "shaders/post_processing/gen5_6/rgbx_load_save_nv12.g6b" +}; + +static const uint32_t pp_nv12_load_save_rgbx_gen6[][4] = { +#include "shaders/post_processing/gen5_6/nv12_load_save_rgbx.g6b" +}; + static struct pp_module pp_modules_gen6[] = { { { @@ -344,7 +475,7 @@ static struct pp_module pp_modules_gen6[] = { NULL, }, - pp_nv12_scaling_initialize, + gen6_nv12_scaling_initialize, }, { @@ -356,7 +487,7 @@ static struct pp_module pp_modules_gen6[] = { NULL, }, - pp_nv12_avs_initialize, + pp_nv12_avs_initialize_nlas, }, { @@ -382,6 +513,77 @@ static struct pp_module pp_modules_gen6[] = { pp_nv12_dn_initialize, }, + { + { + "NV12_PA module", + PP_NV12_LOAD_SAVE_PA, + pp_nv12_load_save_pa_gen6, + sizeof(pp_nv12_load_save_pa_gen6), + NULL, + }, + + pp_plx_load_save_plx_initialize, + }, + + { + { + "PL3_PA module", + PP_PL3_LOAD_SAVE_PA, + pp_pl3_load_save_pa_gen6, + sizeof(pp_pl3_load_save_pa_gen6), + NULL, + }, + + pp_plx_load_save_plx_initialize, + }, + + { + { + "PA_NV12 module", + PP_PA_LOAD_SAVE_NV12, + pp_pa_load_save_nv12_gen6, + sizeof(pp_pa_load_save_nv12_gen6), + NULL, + }, + + pp_plx_load_save_plx_initialize, + }, + + { + { + "PA_PL3 module", + PP_PA_LOAD_SAVE_PL3, + pp_pa_load_save_pl3_gen6, + sizeof(pp_pa_load_save_pl3_gen6), + NULL, + }, + + pp_plx_load_save_plx_initialize, + }, + + { + { + "RGBX_NV12 module", + PP_RGBX_LOAD_SAVE_NV12, + pp_rgbx_load_save_nv12_gen6, + sizeof(pp_rgbx_load_save_nv12_gen6), + NULL, + }, + + pp_plx_load_save_plx_initialize, + }, + + { + { + "NV12_RGBX module", + PP_NV12_LOAD_SAVE_RGBX, + pp_nv12_load_save_rgbx_gen6, + sizeof(pp_nv12_load_save_rgbx_gen6), + NULL, + }, + + pp_plx_load_save_plx_initialize, + }, }; static const uint32_t pp_null_gen7[][4] = { @@ -416,6 +618,24 @@ static const uint32_t pp_nv12_dndi_gen7[][4] = { }; static const uint32_t pp_nv12_dn_gen7[][4] = { +#include "shaders/post_processing/gen7/nv12_dn_nv12.g7b" +}; +static const uint32_t pp_nv12_load_save_pa_gen7[][4] = { +#include "shaders/post_processing/gen7/pl2_to_pa.g7b" +}; +static const uint32_t pp_pl3_load_save_pa_gen7[][4] = { +#include "shaders/post_processing/gen7/pl3_to_pa.g7b" +}; +static const uint32_t pp_pa_load_save_nv12_gen7[][4] = { +#include "shaders/post_processing/gen7/pa_to_pl2.g7b" +}; +static const uint32_t pp_pa_load_save_pl3_gen7[][4] = { +#include "shaders/post_processing/gen7/pa_to_pl3.g7b" +}; +static const uint32_t pp_rgbx_load_save_nv12_gen7[][4] = { +}; +static const uint32_t pp_nv12_load_save_rgbx_gen7[][4] = { +#include "shaders/post_processing/gen7/pl2_to_rgbx.g7b" }; static VAStatus gen7_pp_plx_avs_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context, @@ -545,6 +765,311 @@ static struct pp_module pp_modules_gen7[] = { gen7_pp_nv12_dn_initialize, }, + { + { + "NV12_PA module", + PP_NV12_LOAD_SAVE_PA, + pp_nv12_load_save_pa_gen7, + sizeof(pp_nv12_load_save_pa_gen7), + NULL, + }, + + gen7_pp_plx_avs_initialize, + }, + + { + { + "PL3_PA module", + PP_PL3_LOAD_SAVE_PA, + pp_pl3_load_save_pa_gen7, + sizeof(pp_pl3_load_save_pa_gen7), + NULL, + }, + + gen7_pp_plx_avs_initialize, + }, + + { + { + "PA_NV12 module", + PP_PA_LOAD_SAVE_NV12, + pp_pa_load_save_nv12_gen7, + sizeof(pp_pa_load_save_nv12_gen7), + NULL, + }, + + gen7_pp_plx_avs_initialize, + }, + + { + { + "PA_PL3 module", + PP_PA_LOAD_SAVE_PL3, + pp_pa_load_save_pl3_gen7, + sizeof(pp_pa_load_save_pl3_gen7), + NULL, + }, + + gen7_pp_plx_avs_initialize, + }, + + { + { + "RGBX_NV12 module", + PP_RGBX_LOAD_SAVE_NV12, + pp_rgbx_load_save_nv12_gen7, + sizeof(pp_rgbx_load_save_nv12_gen7), + NULL, + }, + + pp_plx_load_save_plx_initialize, + }, + + { + { + "NV12_RGBX module", + PP_NV12_LOAD_SAVE_RGBX, + pp_nv12_load_save_rgbx_gen7, + sizeof(pp_nv12_load_save_rgbx_gen7), + NULL, + }, + + gen7_pp_plx_avs_initialize, + }, + +}; + +static const uint32_t pp_null_gen75[][4] = { +}; + +static const uint32_t pp_nv12_load_save_nv12_gen75[][4] = { +#include "shaders/post_processing/gen7/pl2_to_pl2.g75b" +}; + +static const uint32_t pp_nv12_load_save_pl3_gen75[][4] = { +#include "shaders/post_processing/gen7/pl2_to_pl3.g75b" +}; + +static const uint32_t pp_pl3_load_save_nv12_gen75[][4] = { +#include "shaders/post_processing/gen7/pl3_to_pl2.g75b" +}; + +static const uint32_t pp_pl3_load_save_pl3_gen75[][4] = { +#include "shaders/post_processing/gen7/pl3_to_pl3.g75b" +}; + +static const uint32_t pp_nv12_scaling_gen75[][4] = { +#include "shaders/post_processing/gen7/avs.g75b" +}; + +static const uint32_t pp_nv12_avs_gen75[][4] = { +#include "shaders/post_processing/gen7/avs.g75b" +}; + +static const uint32_t pp_nv12_dndi_gen75[][4] = { +// #include "shaders/post_processing/gen7/dndi.g75b" +}; + +static const uint32_t pp_nv12_dn_gen75[][4] = { +// #include "shaders/post_processing/gen7/nv12_dn_nv12.g75b" +}; +static const uint32_t pp_nv12_load_save_pa_gen75[][4] = { +#include "shaders/post_processing/gen7/pl2_to_pa.g75b" +}; +static const uint32_t pp_pl3_load_save_pa_gen75[][4] = { +#include "shaders/post_processing/gen7/pl3_to_pa.g75b" +}; +static const uint32_t pp_pa_load_save_nv12_gen75[][4] = { +#include "shaders/post_processing/gen7/pa_to_pl2.g75b" +}; +static const uint32_t pp_pa_load_save_pl3_gen75[][4] = { +#include "shaders/post_processing/gen7/pa_to_pl3.g75b" +}; +static const uint32_t pp_rgbx_load_save_nv12_gen75[][4] = { +}; +static const uint32_t pp_nv12_load_save_rgbx_gen75[][4] = { +}; + +static struct pp_module pp_modules_gen75[] = { + { + { + "NULL module (for testing)", + PP_NULL, + pp_null_gen75, + sizeof(pp_null_gen75), + NULL, + }, + + pp_null_initialize, + }, + + { + { + "NV12_NV12", + PP_NV12_LOAD_SAVE_N12, + pp_nv12_load_save_nv12_gen75, + sizeof(pp_nv12_load_save_nv12_gen75), + NULL, + }, + + gen7_pp_plx_avs_initialize, + }, + + { + { + "NV12_PL3", + PP_NV12_LOAD_SAVE_PL3, + pp_nv12_load_save_pl3_gen75, + sizeof(pp_nv12_load_save_pl3_gen75), + NULL, + }, + + gen7_pp_plx_avs_initialize, + }, + + { + { + "PL3_NV12", + PP_PL3_LOAD_SAVE_N12, + pp_pl3_load_save_nv12_gen75, + sizeof(pp_pl3_load_save_nv12_gen75), + NULL, + }, + + gen7_pp_plx_avs_initialize, + }, + + { + { + "PL3_PL3", + PP_PL3_LOAD_SAVE_N12, + pp_pl3_load_save_pl3_gen75, + sizeof(pp_pl3_load_save_pl3_gen75), + NULL, + }, + + gen7_pp_plx_avs_initialize, + }, + + { + { + "NV12 Scaling module", + PP_NV12_SCALING, + pp_nv12_scaling_gen75, + sizeof(pp_nv12_scaling_gen75), + NULL, + }, + + gen7_pp_plx_avs_initialize, + }, + + { + { + "NV12 AVS module", + PP_NV12_AVS, + pp_nv12_avs_gen75, + sizeof(pp_nv12_avs_gen75), + NULL, + }, + + gen7_pp_plx_avs_initialize, + }, + + { + { + "NV12 DNDI module", + PP_NV12_DNDI, + pp_nv12_dndi_gen75, + sizeof(pp_nv12_dndi_gen75), + NULL, + }, + + gen7_pp_nv12_dndi_initialize, + }, + + { + { + "NV12 DN module", + PP_NV12_DN, + pp_nv12_dn_gen75, + sizeof(pp_nv12_dn_gen75), + NULL, + }, + + gen7_pp_nv12_dn_initialize, + }, + { + { + "NV12_PA module", + PP_NV12_LOAD_SAVE_PA, + pp_nv12_load_save_pa_gen75, + sizeof(pp_nv12_load_save_pa_gen75), + NULL, + }, + + gen7_pp_plx_avs_initialize, + }, + + { + { + "PL3_PA module", + PP_PL3_LOAD_SAVE_PA, + pp_pl3_load_save_pa_gen75, + sizeof(pp_pl3_load_save_pa_gen75), + NULL, + }, + + gen7_pp_plx_avs_initialize, + }, + + { + { + "PA_NV12 module", + PP_PA_LOAD_SAVE_NV12, + pp_pa_load_save_nv12_gen75, + sizeof(pp_pa_load_save_nv12_gen75), + NULL, + }, + + gen7_pp_plx_avs_initialize, + }, + + { + { + "PA_PL3 module", + PP_PA_LOAD_SAVE_PL3, + pp_pa_load_save_pl3_gen75, + sizeof(pp_pa_load_save_pl3_gen75), + NULL, + }, + + gen7_pp_plx_avs_initialize, + }, + + { + { + "RGBX_NV12 module", + PP_RGBX_LOAD_SAVE_NV12, + pp_rgbx_load_save_nv12_gen75, + sizeof(pp_rgbx_load_save_nv12_gen75), + NULL, + }, + + pp_plx_load_save_plx_initialize, + }, + + { + { + "NV12_RGBX module", + PP_NV12_LOAD_SAVE_RGBX, + pp_nv12_load_save_rgbx_gen75, + sizeof(pp_nv12_load_save_rgbx_gen75), + NULL, + }, + + pp_plx_load_save_plx_initialize, + }, + }; static int @@ -863,6 +1388,69 @@ ironlake_pp_pipeline_setup(VADriverContextP ctx, intel_batchbuffer_end_atomic(batch); } +// update u/v offset when the surface format are packed yuv +static void i965_update_src_surface_static_parameter( + VADriverContextP ctx, + struct i965_post_processing_context *pp_context, + const struct i965_surface *surface) +{ + struct pp_static_parameter *pp_static_parameter = pp_context->pp_static_parameter; + int fourcc = pp_get_surface_fourcc(ctx, surface); + + switch (fourcc) { + case VA_FOURCC('Y', 'U', 'Y', '2'): + pp_static_parameter->grf1.source_packed_u_offset = 1; + pp_static_parameter->grf1.source_packed_v_offset = 3; + break; + case VA_FOURCC('U', 'Y', 'V', 'Y'): + pp_static_parameter->grf1.source_packed_y_offset = 1; + pp_static_parameter->grf1.source_packed_v_offset = 2; + break; + case VA_FOURCC('B', 'G', 'R', 'X'): + case VA_FOURCC('B', 'G', 'R', 'A'): + pp_static_parameter->grf1.source_rgb_layout = 0; + break; + case VA_FOURCC('R', 'G', 'B', 'X'): + case VA_FOURCC('R', 'G', 'B', 'A'): + pp_static_parameter->grf1.source_rgb_layout = 1; + break; + default: + break; + } + +} + +static void i965_update_dst_surface_static_parameter( + VADriverContextP ctx, + struct i965_post_processing_context *pp_context, + const struct i965_surface *surface) +{ + struct pp_static_parameter *pp_static_parameter = pp_context->pp_static_parameter; + int fourcc = pp_get_surface_fourcc(ctx, surface); + + switch (fourcc) { + case VA_FOURCC('Y', 'U', 'Y', '2'): + pp_static_parameter->grf1.r1_2.load_and_save.destination_packed_u_offset = 1; + pp_static_parameter->grf1.r1_2.load_and_save.destination_packed_v_offset = 3; + break; + case VA_FOURCC('U', 'Y', 'V', 'Y'): + pp_static_parameter->grf1.r1_2.load_and_save.destination_packed_y_offset = 1; + pp_static_parameter->grf1.r1_2.load_and_save.destination_packed_v_offset = 2; + break; + case VA_FOURCC('B', 'G', 'R', 'X'): + case VA_FOURCC('B', 'G', 'R', 'A'): + pp_static_parameter->grf1.r1_2.csc.destination_rgb_layout = 0; + break; + case VA_FOURCC('R', 'G', 'B', 'X'): + case VA_FOURCC('R', 'G', 'B', 'A'): + pp_static_parameter->grf1.r1_2.csc.destination_rgb_layout = 1; + break; + default: + break; + } + +} + static void i965_pp_set_surface_state(VADriverContextP ctx, struct i965_post_processing_context *pp_context, dri_bo *surf_bo, unsigned long surf_bo_offset, @@ -944,6 +1532,7 @@ gen7_pp_set_surface_state(VADriverContextP ctx, struct i965_post_processing_cont int width, int height, int pitch, int format, int index, int is_target) { + struct i965_driver_data * const i965 = i965_driver_data(ctx); struct gen7_surface_state *ss; dri_bo *ss_bo; unsigned int tiling; @@ -964,6 +1553,8 @@ gen7_pp_set_surface_state(VADriverContextP ctx, struct i965_post_processing_cont ss->ss2.height = height - 1; ss->ss3.pitch = pitch - 1; gen7_pp_set_surface_tiling(ss, tiling); + if (IS_HASWELL(i965->intel.device_id)) + gen7_render_set_surface_scs(ss); dri_bo_emit_reloc(ss_bo, I915_GEM_DOMAIN_RENDER, is_target ? I915_GEM_DOMAIN_RENDER : 0, surf_bo_offset, @@ -1029,7 +1620,13 @@ pp_set_media_rw_message_surface(VADriverContextP ctx, struct i965_post_processin const int V = fourcc == VA_FOURCC('Y', 'V', '1', '2') ? 1 : 2; const int UV = 1; int interleaved_uv = fourcc == VA_FOURCC('N', 'V', '1', '2'); - + int packed_yuv = (fourcc == VA_FOURCC('Y', 'U', 'Y', '2') || fourcc == VA_FOURCC('U', 'Y', 'V', 'Y')); + int full_packed_format = (fourcc == VA_FOURCC('R', 'G', 'B', 'A') || + fourcc == VA_FOURCC('R', 'G', 'B', 'X') || + fourcc == VA_FOURCC('B', 'G', 'R', 'A') || + fourcc == VA_FOURCC('B', 'G', 'R', 'X')); + int scale_factor_of_1st_plane_width_in_byte = 1; + if (surface->type == I965_SURFACE_TYPE_SURFACE) { obj_surface = SURFACE(surface->id); bo = obj_surface->bo; @@ -1038,7 +1635,15 @@ pp_set_media_rw_message_surface(VADriverContextP ctx, struct i965_post_processin pitch[0] = obj_surface->width; offset[0] = 0; - if (interleaved_uv) { + if (full_packed_format) { + scale_factor_of_1st_plane_width_in_byte = 4; + pitch[0] = obj_surface->width * 4; + } + else if (packed_yuv ) { + scale_factor_of_1st_plane_width_in_byte = 2; + pitch[0] = obj_surface->width * 2; + } + else if (interleaved_uv) { width[1] = obj_surface->orig_width; height[1] = obj_surface->orig_height / 2; pitch[1] = obj_surface->width; @@ -1061,7 +1666,13 @@ pp_set_media_rw_message_surface(VADriverContextP ctx, struct i965_post_processin pitch[0] = obj_image->image.pitches[0]; offset[0] = obj_image->image.offsets[0]; - if (interleaved_uv) { + if (full_packed_format) { + scale_factor_of_1st_plane_width_in_byte = 4; + } + else if (packed_yuv ) { + scale_factor_of_1st_plane_width_in_byte = 2; + } + else if (interleaved_uv) { width[1] = obj_image->image.width; height[1] = obj_image->image.height / 2; pitch[1] = obj_image->image.pitches[1]; @@ -1081,26 +1692,28 @@ pp_set_media_rw_message_surface(VADriverContextP ctx, struct i965_post_processin /* Y surface */ i965_pp_set_surface_state(ctx, pp_context, bo, offset[Y], - width[Y] / 4, height[Y], pitch[Y], I965_SURFACEFORMAT_R8_UNORM, + width[Y] *scale_factor_of_1st_plane_width_in_byte / 4, height[Y], pitch[Y], I965_SURFACEFORMAT_R8_UNORM, base_index, is_target); - if (interleaved_uv) { - i965_pp_set_surface_state(ctx, pp_context, - bo, offset[UV], - width[UV] / 4, height[UV], pitch[UV], I965_SURFACEFORMAT_R8_UNORM, - base_index + 1, is_target); - } else { - /* U surface */ - i965_pp_set_surface_state(ctx, pp_context, - bo, offset[U], - width[U] / 4, height[U], pitch[U], I965_SURFACEFORMAT_R8_UNORM, - base_index + 1, is_target); - - /* V surface */ - i965_pp_set_surface_state(ctx, pp_context, - bo, offset[V], - width[V] / 4, height[V], pitch[V], I965_SURFACEFORMAT_R8_UNORM, - base_index + 2, is_target); + if (!packed_yuv && !full_packed_format) { + if (interleaved_uv) { + i965_pp_set_surface_state(ctx, pp_context, + bo, offset[UV], + width[UV] / 4, height[UV], pitch[UV], I965_SURFACEFORMAT_R8_UNORM, + base_index + 1, is_target); + } else { + /* U surface */ + i965_pp_set_surface_state(ctx, pp_context, + bo, offset[U], + width[U] / 4, height[U], pitch[U], I965_SURFACEFORMAT_R8_UNORM, + base_index + 1, is_target); + + /* V surface */ + i965_pp_set_surface_state(ctx, pp_context, + bo, offset[V], + width[V] / 4, height[V], pitch[V], I965_SURFACEFORMAT_R8_UNORM, + base_index + 2, is_target); + } } } @@ -1121,6 +1734,11 @@ gen7_pp_set_media_rw_message_surface(VADriverContextP ctx, struct i965_post_proc const int V = (fourcc == VA_FOURCC('Y', 'V', '1', '2') || fourcc == VA_FOURCC('I', 'M', 'C', '1')) ? 1 : 2; int interleaved_uv = fourcc == VA_FOURCC('N', 'V', '1', '2'); + int packed_yuv = (fourcc == VA_FOURCC('Y', 'U', 'Y', '2') || fourcc == VA_FOURCC('U', 'Y', 'V', 'Y')); + int rgbx_format = (fourcc == VA_FOURCC('R', 'G', 'B', 'A') || + fourcc == VA_FOURCC('R', 'G', 'B', 'X') || + fourcc == VA_FOURCC('B', 'G', 'R', 'A') || + fourcc == VA_FOURCC('B', 'G', 'R', 'X')); if (surface->type == I965_SURFACE_TYPE_SURFACE) { obj_surface = SURFACE(surface->id); @@ -1130,6 +1748,18 @@ gen7_pp_set_media_rw_message_surface(VADriverContextP ctx, struct i965_post_proc pitch[0] = obj_surface->width; offset[0] = 0; + if (packed_yuv) { + if (is_target) + width[0] = obj_surface->orig_width * 2; /* surface format is R8, so double the width */ + else + width[0] = obj_surface->orig_width; /* surface foramt is YCBCR, width is specified in units of pixels */ + + pitch[0] = obj_surface->width * 2; + } else if (rgbx_format) { + if (is_target) + width[0] = obj_surface->orig_width * 4; /* surface format is R8, so quad the width */ + } + width[1] = obj_surface->cb_cr_width; height[1] = obj_surface->cb_cr_height; pitch[1] = obj_surface->cb_cr_pitch; @@ -1147,8 +1777,16 @@ gen7_pp_set_media_rw_message_surface(VADriverContextP ctx, struct i965_post_proc pitch[0] = obj_image->image.pitches[0]; offset[0] = obj_image->image.offsets[0]; - if (interleaved_uv) { - width[1] = obj_image->image.width; + if (rgbx_format) { + if (is_target) + width[0] = obj_image->image.width * 4; /* surface format is R8, so quad the width */ + } else if (packed_yuv) { + if (is_target) + width[0] = obj_image->image.width * 2; /* surface format is R8, so double the width */ + else + width[0] = obj_image->image.width; /* surface foramt is YCBCR, width is specified in units of pixels */ + } else if (interleaved_uv) { + width[1] = obj_image->image.width / 2; height[1] = obj_image->image.height / 2; pitch[1] = obj_image->image.pitches[1]; offset[1] = obj_image->image.offsets[1]; @@ -1168,55 +1806,83 @@ gen7_pp_set_media_rw_message_surface(VADriverContextP ctx, struct i965_post_proc gen7_pp_set_surface_state(ctx, pp_context, bo, 0, width[0] / 4, height[0], pitch[0], - I965_SURFACEFORMAT_R8_SINT, + I965_SURFACEFORMAT_R8_UINT, base_index, 1); - - if (interleaved_uv) { - gen7_pp_set_surface_state(ctx, pp_context, - bo, offset[1], - width[1] / 2, height[1], pitch[1], - I965_SURFACEFORMAT_R8G8_SINT, - base_index + 1, 1); - } else { - gen7_pp_set_surface_state(ctx, pp_context, - bo, offset[1], - width[1] / 4, height[1], pitch[1], - I965_SURFACEFORMAT_R8_SINT, - base_index + 1, 1); - gen7_pp_set_surface_state(ctx, pp_context, - bo, offset[2], - width[2] / 4, height[2], pitch[2], - I965_SURFACEFORMAT_R8_SINT, - base_index + 2, 1); + if (rgbx_format) { + struct gen7_pp_static_parameter *pp_static_parameter = pp_context->pp_static_parameter; + /* the format is MSB: X-B-G-R */ + pp_static_parameter->grf2.save_avs_rgb_swap = 0; + if ((fourcc == VA_FOURCC('B', 'G', 'R', 'A')) || + (fourcc == VA_FOURCC('B', 'G', 'R', 'X'))) { + /* It is stored as MSB: X-R-G-B */ + pp_static_parameter->grf2.save_avs_rgb_swap = 1; + } + } + if (!packed_yuv && !rgbx_format) { + if (interleaved_uv) { + gen7_pp_set_surface_state(ctx, pp_context, + bo, offset[1], + width[1] / 2, height[1], pitch[1], + I965_SURFACEFORMAT_R8G8_SINT, + base_index + 1, 1); + } else { + gen7_pp_set_surface_state(ctx, pp_context, + bo, offset[1], + width[1] / 4, height[1], pitch[1], + I965_SURFACEFORMAT_R8_SINT, + base_index + 1, 1); + gen7_pp_set_surface_state(ctx, pp_context, + bo, offset[2], + width[2] / 4, height[2], pitch[2], + I965_SURFACEFORMAT_R8_SINT, + base_index + 2, 1); + } } } else { + int format0 = SURFACE_FORMAT_Y8_UNORM; + + switch (fourcc) { + case VA_FOURCC('Y', 'U', 'Y', '2'): + format0 = SURFACE_FORMAT_YCRCB_NORMAL; + break; + + case VA_FOURCC('U', 'Y', 'V', 'Y'): + format0 = SURFACE_FORMAT_YCRCB_SWAPY; + break; + + default: + break; + } + gen7_pp_set_surface2_state(ctx, pp_context, bo, offset[0], width[0], height[0], pitch[0], 0, 0, - SURFACE_FORMAT_Y8_UNORM, 0, + format0, 0, base_index); - if (interleaved_uv) { - gen7_pp_set_surface2_state(ctx, pp_context, - bo, offset[1], - width[1], height[1], pitch[1], - 0, 0, - SURFACE_FORMAT_R8B8_UNORM, 0, - base_index + 1); - } else { - gen7_pp_set_surface2_state(ctx, pp_context, - bo, offset[1], - width[1], height[1], pitch[1], - 0, 0, - SURFACE_FORMAT_R8_UNORM, 0, - base_index + 1); - gen7_pp_set_surface2_state(ctx, pp_context, - bo, offset[2], - width[2], height[2], pitch[2], - 0, 0, - SURFACE_FORMAT_R8_UNORM, 0, - base_index + 2); + if (!packed_yuv) { + if (interleaved_uv) { + gen7_pp_set_surface2_state(ctx, pp_context, + bo, offset[1], + width[1], height[1], pitch[1], + 0, 0, + SURFACE_FORMAT_R8B8_UNORM, 0, + base_index + 1); + } else { + gen7_pp_set_surface2_state(ctx, pp_context, + bo, offset[1], + width[1], height[1], pitch[1], + 0, 0, + SURFACE_FORMAT_R8_UNORM, 0, + base_index + 1); + gen7_pp_set_surface2_state(ctx, pp_context, + bo, offset[2], + width[2], height[2], pitch[2], + 0, 0, + SURFACE_FORMAT_R8_UNORM, 0, + base_index + 2); + } } } } @@ -1275,15 +1941,47 @@ static int pp_load_save_set_block_parameter(struct i965_post_processing_context *pp_context, int x, int y) { struct pp_inline_parameter *pp_inline_parameter = pp_context->pp_inline_parameter; + struct pp_load_save_context *pp_load_save_context = (struct pp_load_save_context *)&pp_context->private_context; - pp_inline_parameter->grf5.block_vertical_mask = 0xff; - pp_inline_parameter->grf5.block_horizontal_mask = 0xffff; - pp_inline_parameter->grf5.destination_block_horizontal_origin = x * 16; - pp_inline_parameter->grf5.destination_block_vertical_origin = y * 8; + pp_inline_parameter->grf5.destination_block_horizontal_origin = x * 16 + pp_load_save_context->dest_x; + pp_inline_parameter->grf5.destination_block_vertical_origin = y * 8 + pp_load_save_context->dest_y; return 0; } +static void calculate_boundary_block_mask(struct i965_post_processing_context *pp_context, const VARectangle *dst_rect) +{ + int i; + /* x offset of dest surface must be dword aligned. + * so we have to extend dst surface on left edge, and mask out pixels not interested + */ + if (dst_rect->x%GPU_ASM_X_OFFSET_ALIGNMENT) { + pp_context->block_horizontal_mask_left = 0; + for (i=dst_rect->x%GPU_ASM_X_OFFSET_ALIGNMENT; iblock_horizontal_mask_left |= 1<block_horizontal_mask_left = 0xffff; + } + + int dst_width_adjust = dst_rect->width + dst_rect->x%GPU_ASM_X_OFFSET_ALIGNMENT; + if (dst_width_adjust%GPU_ASM_BLOCK_WIDTH){ + pp_context->block_horizontal_mask_right = (1 << (dst_width_adjust%GPU_ASM_BLOCK_WIDTH)) - 1; + } + else { + pp_context->block_horizontal_mask_right = 0xffff; + } + + if (dst_rect->height%GPU_ASM_BLOCK_HEIGHT){ + pp_context->block_vertical_mask_bottom = (1 << (dst_rect->height%GPU_ASM_BLOCK_HEIGHT)) - 1; + } + else { + pp_context->block_vertical_mask_bottom = 0xff; + } + +} static VAStatus pp_plx_load_save_plx_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context, const struct i965_surface *src_surface, @@ -1294,6 +1992,7 @@ pp_plx_load_save_plx_initialize(VADriverContextP ctx, struct i965_post_processin { struct pp_load_save_context *pp_load_save_context = (struct pp_load_save_context *)&pp_context->private_context; struct pp_inline_parameter *pp_inline_parameter = pp_context->pp_inline_parameter; + struct pp_static_parameter *pp_static_parameter = pp_context->pp_static_parameter; int width[3], height[3], pitch[3], offset[3]; const int Y = 0; @@ -1309,11 +2008,22 @@ pp_plx_load_save_plx_initialize(VADriverContextP ctx, struct i965_post_processin pp_context->pp_x_steps = pp_load_save_x_steps; pp_context->pp_y_steps = pp_load_save_y_steps; pp_context->pp_set_block_parameter = pp_load_save_set_block_parameter; - pp_load_save_context->dest_h = ALIGN(height[Y], 16); - pp_load_save_context->dest_w = ALIGN(width[Y], 16); - pp_inline_parameter->grf5.block_count_x = ALIGN(width[Y], 16) / 16; /* 1 x N */ - pp_inline_parameter->grf5.number_blocks = ALIGN(width[Y], 16) / 16; + int dst_left_edge_extend = dst_rect->x%GPU_ASM_X_OFFSET_ALIGNMENT;; + pp_load_save_context->dest_x = dst_rect->x - dst_left_edge_extend; + pp_load_save_context->dest_y = dst_rect->y; + pp_load_save_context->dest_h = ALIGN(dst_rect->height, 8); + pp_load_save_context->dest_w = ALIGN(dst_rect->width+dst_left_edge_extend, 16); + + pp_inline_parameter->grf5.block_count_x = pp_load_save_context->dest_w / 16; /* 1 x N */ + pp_inline_parameter->grf5.number_blocks = pp_load_save_context->dest_w / 16; + + pp_static_parameter->grf3.horizontal_origin_offset = src_rect->x; + pp_static_parameter->grf3.vertical_origin_offset = src_rect->y; + + // update u/v offset for packed yuv + i965_update_src_surface_static_parameter (ctx, pp_context, src_surface); + i965_update_dst_surface_static_parameter (ctx, pp_context, dst_surface); dst_surface->flags = src_surface->flags; @@ -1432,20 +2142,20 @@ pp_nv12_scaling_initialize(VADriverContextP ctx, struct i965_post_processing_con pp_context->pp_y_steps = pp_scaling_y_steps; pp_context->pp_set_block_parameter = pp_scaling_set_block_parameter; - pp_scaling_context->dest_x = dst_rect->x; + int dst_left_edge_extend = dst_rect->x%GPU_ASM_X_OFFSET_ALIGNMENT; + float src_left_edge_extend = (float)dst_left_edge_extend*src_rect->width/dst_rect->width; + pp_scaling_context->dest_x = dst_rect->x - dst_left_edge_extend; pp_scaling_context->dest_y = dst_rect->y; - pp_scaling_context->dest_w = ALIGN(dst_rect->width, 16); - pp_scaling_context->dest_h = ALIGN(dst_rect->height, 16); - pp_scaling_context->src_normalized_x = (float)src_rect->x / in_w; + pp_scaling_context->dest_w = ALIGN(dst_rect->width + dst_left_edge_extend, 16); + pp_scaling_context->dest_h = ALIGN(dst_rect->height, 8); + pp_scaling_context->src_normalized_x = (float)(src_rect->x - src_left_edge_extend)/ in_w; pp_scaling_context->src_normalized_y = (float)src_rect->y / in_h; pp_static_parameter->grf1.r1_6.normalized_video_y_scaling_step = (float) src_rect->height / in_h / dst_rect->height; - pp_inline_parameter->grf5.normalized_video_x_scaling_step = (float) src_rect->width / in_w / dst_rect->width; + pp_inline_parameter->grf5.normalized_video_x_scaling_step = (float) (src_rect->width + src_left_edge_extend)/ in_w / (dst_rect->width + dst_left_edge_extend); pp_inline_parameter->grf5.block_count_x = pp_scaling_context->dest_w / 16; /* 1 x N */ pp_inline_parameter->grf5.number_blocks = pp_scaling_context->dest_w / 16; - pp_inline_parameter->grf5.block_vertical_mask = 0xff; - pp_inline_parameter->grf5.block_horizontal_mask = 0xffff; dst_surface->flags = src_surface->flags; @@ -1475,7 +2185,10 @@ pp_avs_set_block_parameter(struct i965_post_processing_context *pp_context, int float src_x_steping, src_y_steping, video_step_delta; int tmp_w = ALIGN(pp_avs_context->dest_h * pp_avs_context->src_w / pp_avs_context->src_h, 16); - if (tmp_w >= pp_avs_context->dest_w) { + if (pp_static_parameter->grf4.r4_2.avs.nlas == 0) { + src_x_steping = pp_inline_parameter->grf5.normalized_video_x_scaling_step; + pp_inline_parameter->grf5.r5_1.source_surface_block_normalized_horizontal_origin = src_x_steping * x * 16 + pp_avs_context->src_normalized_x; + } else if (tmp_w >= pp_avs_context->dest_w) { pp_inline_parameter->grf5.normalized_video_x_scaling_step = 1.0 / tmp_w; pp_inline_parameter->grf6.video_step_delta = 0; @@ -1570,7 +2283,8 @@ pp_nv12_avs_initialize(VADriverContextP ctx, struct i965_post_processing_context const VARectangle *src_rect, struct i965_surface *dst_surface, const VARectangle *dst_rect, - void *filter_param) + void *filter_param, + int nlas) { struct i965_driver_data *i965 = i965_driver_data(ctx); struct pp_avs_context *pp_avs_context = (struct pp_avs_context *)&pp_context->private_context; @@ -1818,23 +2532,23 @@ pp_nv12_avs_initialize(VADriverContextP ctx, struct i965_post_processing_context pp_context->pp_y_steps = pp_avs_y_steps; pp_context->pp_set_block_parameter = pp_avs_set_block_parameter; - pp_avs_context->dest_x = dst_rect->x; + int dst_left_edge_extend = dst_rect->x%GPU_ASM_X_OFFSET_ALIGNMENT; + float src_left_edge_extend = (float)dst_left_edge_extend*src_rect->width/dst_rect->width; + pp_avs_context->dest_x = dst_rect->x - dst_left_edge_extend; pp_avs_context->dest_y = dst_rect->y; - pp_avs_context->dest_w = ALIGN(dst_rect->width, 16); - pp_avs_context->dest_h = ALIGN(dst_rect->height, 16); - pp_avs_context->src_normalized_x = (float)src_rect->x / in_w; + pp_avs_context->dest_w = ALIGN(dst_rect->width + dst_left_edge_extend, 16); + pp_avs_context->dest_h = ALIGN(dst_rect->height, 8); + pp_avs_context->src_normalized_x = (float)(src_rect->x - src_left_edge_extend)/ in_w; pp_avs_context->src_normalized_y = (float)src_rect->y / in_h; - pp_avs_context->src_w = src_rect->width; + pp_avs_context->src_w = src_rect->width + src_left_edge_extend; pp_avs_context->src_h = src_rect->height; - pp_static_parameter->grf4.r4_2.avs.nlas = 1; + pp_static_parameter->grf4.r4_2.avs.nlas = nlas; pp_static_parameter->grf1.r1_6.normalized_video_y_scaling_step = (float) src_rect->height / in_h / dst_rect->height; - pp_inline_parameter->grf5.normalized_video_x_scaling_step = (float) src_rect->width / in_w / dst_rect->width; + pp_inline_parameter->grf5.normalized_video_x_scaling_step = (float) (src_rect->width + src_left_edge_extend)/ in_w / (dst_rect->width + dst_left_edge_extend); pp_inline_parameter->grf5.block_count_x = 1; /* M x 1 */ pp_inline_parameter->grf5.number_blocks = pp_avs_context->dest_h / 8; - pp_inline_parameter->grf5.block_vertical_mask = 0xff; - pp_inline_parameter->grf5.block_horizontal_mask = 0xffff; pp_inline_parameter->grf6.video_step_delta = 0.0; dst_surface->flags = src_surface->flags; @@ -1842,6 +2556,40 @@ pp_nv12_avs_initialize(VADriverContextP ctx, struct i965_post_processing_context return VA_STATUS_SUCCESS; } +static VAStatus +pp_nv12_avs_initialize_nlas(VADriverContextP ctx, struct i965_post_processing_context *pp_context, + const struct i965_surface *src_surface, + const VARectangle *src_rect, + struct i965_surface *dst_surface, + const VARectangle *dst_rect, + void *filter_param) +{ + return pp_nv12_avs_initialize(ctx, pp_context, + src_surface, + src_rect, + dst_surface, + dst_rect, + filter_param, + 1); +} + +static VAStatus +gen6_nv12_scaling_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context, + const struct i965_surface *src_surface, + const VARectangle *src_rect, + struct i965_surface *dst_surface, + const VARectangle *dst_rect, + void *filter_param) +{ + return pp_nv12_avs_initialize(ctx, pp_context, + src_surface, + src_rect, + dst_surface, + dst_rect, + filter_param, + 0); +} + static int gen7_pp_avs_x_steps(void *private_context) { @@ -1872,6 +2620,24 @@ gen7_pp_avs_set_block_parameter(struct i965_post_processing_context *pp_context, return 0; } +static void gen7_update_src_surface_uv_offset(VADriverContextP ctx, + struct i965_post_processing_context *pp_context, + const struct i965_surface *surface) +{ + struct gen7_pp_static_parameter *pp_static_parameter = pp_context->pp_static_parameter; + int fourcc = pp_get_surface_fourcc(ctx, surface); + + if (fourcc == VA_FOURCC('Y', 'U', 'Y', '2')) { + pp_static_parameter->grf2.di_destination_packed_y_component_offset = 0; + pp_static_parameter->grf2.di_destination_packed_u_component_offset = 1; + pp_static_parameter->grf2.di_destination_packed_v_component_offset = 3; + } else if (fourcc == VA_FOURCC('U', 'Y', 'V', 'Y')) { + pp_static_parameter->grf2.di_destination_packed_y_component_offset = 1; + pp_static_parameter->grf2.di_destination_packed_u_component_offset = 0; + pp_static_parameter->grf2.di_destination_packed_v_component_offset = 2; + } +} + static VAStatus gen7_pp_plx_avs_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context, const struct i965_surface *src_surface, @@ -1886,10 +2652,13 @@ gen7_pp_plx_avs_initialize(VADriverContextP ctx, struct i965_post_processing_con struct i965_sampler_8x8_state *sampler_8x8_state; int index, i; int width[3], height[3], pitch[3], offset[3]; + int src_width, src_height; /* source surface */ gen7_pp_set_media_rw_message_surface(ctx, pp_context, src_surface, 0, 0, width, height, pitch, offset); + src_width = width[0]; + src_height = height[0]; /* destination surface */ gen7_pp_set_media_rw_message_surface(ctx, pp_context, dst_surface, 24, 1, @@ -2048,11 +2817,21 @@ gen7_pp_plx_avs_initialize(VADriverContextP ctx, struct i965_post_processing_con pp_avs_context->src_w = src_rect->width; pp_avs_context->src_h = src_rect->height; + int dw = (pp_avs_context->src_w - 1) / 16 + 1; + dw = MAX(dw, pp_avs_context->dest_w); + pp_static_parameter->grf1.pointer_to_inline_parameter = 7; - pp_static_parameter->grf3.sampler_load_horizontal_scaling_step_ratio = (float) pp_avs_context->src_w / pp_avs_context->dest_w; - pp_static_parameter->grf4.sampler_load_vertical_scaling_step = (float) 1.0 / pp_avs_context->dest_h; + pp_static_parameter->grf2.avs_wa_enable = 1; /* must be set for GEN7 */ + pp_static_parameter->grf2.avs_wa_width = dw; + pp_static_parameter->grf2.avs_wa_one_div_256_width = (float) 1.0 / (256 * dw); + pp_static_parameter->grf2.avs_wa_five_div_256_width = (float) 5.0 / (256 * dw); + + pp_static_parameter->grf3.sampler_load_horizontal_scaling_step_ratio = (float) pp_avs_context->src_w / dw; + pp_static_parameter->grf4.sampler_load_vertical_scaling_step = (float) src_rect->height / src_height / pp_avs_context->dest_h; pp_static_parameter->grf5.sampler_load_vertical_frame_origin = -(float)pp_avs_context->dest_y / pp_avs_context->dest_h; - pp_static_parameter->grf6.sampler_load_horizontal_frame_origin = -(float)pp_avs_context->dest_x / pp_avs_context->dest_w; + pp_static_parameter->grf6.sampler_load_horizontal_frame_origin = -(float)pp_avs_context->dest_x / dw; + + gen7_update_src_surface_uv_offset(ctx, pp_context, dst_surface); dst_surface->flags = src_surface->flags; @@ -2685,7 +3464,9 @@ gen7_pp_nv12_dndi_initialize(VADriverContextP ctx, struct i965_post_processing_c static int gen7_pp_dn_x_steps(void *private_context) { - return 1; + struct pp_dn_context *pp_dn_context = private_context; + + return pp_dn_context->dest_w / 16; } static int @@ -2780,7 +3561,15 @@ gen7_pp_nv12_dn_initialize(VADriverContextP ctx, struct i965_post_processing_con SURFACE_FORMAT_PLANAR_420_8, 1, 3); - /* source STMM surface index 5 */ + /* source (temporal reference) YUV surface index 4 */ + gen7_pp_set_surface2_state(ctx, pp_context, + obj_surface->bo, 0, + orig_w, orig_h, w, + 0, h, + SURFACE_FORMAT_PLANAR_420_8, 1, + 4); + + /* STMM / History Statistics input surface, index 5 */ gen7_pp_set_surface_state(ctx, pp_context, pp_context->stmm.bo, 0, orig_w, orig_h, w, I965_SURFACEFORMAT_R8_UNORM, @@ -2793,17 +3582,18 @@ gen7_pp_nv12_dn_initialize(VADriverContextP ctx, struct i965_post_processing_con w = obj_surface->width; h = obj_surface->height; - /* destination Y surface index 7 */ + /* destination Y surface index 24 */ gen7_pp_set_surface_state(ctx, pp_context, obj_surface->bo, 0, orig_w / 4, orig_h, w, I965_SURFACEFORMAT_R8_UNORM, - 7, 1); + 24, 1); - /* destination UV surface index 8 */ + /* destination UV surface index 25 */ gen7_pp_set_surface_state(ctx, pp_context, obj_surface->bo, w * h, orig_w / 4, orig_h / 2, w, I965_SURFACEFORMAT_R8G8_UNORM, - 8, 1); + 25, 1); + /* sampler dn */ dri_bo_map(pp_context->sampler_state_table.bo, True); assert(pp_context->sampler_state_table.bo->virtual); @@ -2977,16 +3767,12 @@ ironlake_pp_initialize( assert(bo); pp_context->vfe_state.bo = bo; - if (IS_GEN7(i965->intel.device_id)) { - static_param_size = sizeof(struct gen7_pp_static_parameter); - inline_param_size = sizeof(struct gen7_pp_inline_parameter); - } else { - static_param_size = sizeof(struct pp_static_parameter); - inline_param_size = sizeof(struct pp_inline_parameter); - } + static_param_size = sizeof(struct pp_static_parameter); + inline_param_size = sizeof(struct pp_inline_parameter); memset(pp_context->pp_static_parameter, 0, static_param_size); memset(pp_context->pp_inline_parameter, 0, inline_param_size); + assert(pp_index >= PP_NULL && pp_index < NUM_PP_MODULES); pp_context->current_pp = pp_index; pp_module = &pp_context->pp_modules[pp_index]; @@ -3050,8 +3836,7 @@ gen6_pp_initialize( struct i965_driver_data *i965 = i965_driver_data(ctx); struct pp_module *pp_module; dri_bo *bo; - struct pp_inline_parameter *pp_inline_parameter = pp_context->pp_inline_parameter; - struct pp_static_parameter *pp_static_parameter = pp_context->pp_static_parameter; + int static_param_size, inline_param_size; dri_bo_unreference(pp_context->surface_state_binding_table.bo); bo = dri_bo_alloc(i965->intel.bufmgr, @@ -3113,8 +3898,17 @@ gen6_pp_initialize( assert(bo); pp_context->vfe_state.bo = bo; - memset(pp_static_parameter, 0, sizeof(*pp_static_parameter)); - memset(pp_inline_parameter, 0, sizeof(*pp_inline_parameter)); + if (IS_GEN7(i965->intel.device_id)) { + static_param_size = sizeof(struct gen7_pp_static_parameter); + inline_param_size = sizeof(struct gen7_pp_inline_parameter); + } else { + static_param_size = sizeof(struct pp_static_parameter); + inline_param_size = sizeof(struct pp_inline_parameter); + } + + memset(pp_context->pp_static_parameter, 0, static_param_size); + memset(pp_context->pp_inline_parameter, 0, inline_param_size); + assert(pp_index >= PP_NULL && pp_index < NUM_PP_MODULES); pp_context->current_pp = pp_index; pp_module = &pp_context->pp_modules[pp_index]; @@ -3129,6 +3923,8 @@ gen6_pp_initialize( else va_status = VA_STATUS_ERROR_UNIMPLEMENTED; + calculate_boundary_block_mask(pp_context, dst_rect); + return va_status; } @@ -3300,6 +4096,46 @@ gen6_interface_descriptor_load(VADriverContextP ctx, ADVANCE_BATCH(batch); } +static void update_block_mask_parameter(struct i965_post_processing_context *pp_context, int x, int y, int x_steps, int y_steps) +{ + struct pp_inline_parameter *pp_inline_parameter = pp_context->pp_inline_parameter; + + pp_inline_parameter->grf5.block_vertical_mask = 0xff; + pp_inline_parameter->grf6.block_vertical_mask_bottom = pp_context->block_vertical_mask_bottom; + // for the first block, it always on the left edge. the second block will reload horizontal_mask from grf6.block_horizontal_mask_middle + pp_inline_parameter->grf5.block_horizontal_mask = pp_context->block_horizontal_mask_left; + pp_inline_parameter->grf6.block_horizontal_mask_middle = 0xffff; + pp_inline_parameter->grf6.block_horizontal_mask_right = pp_context->block_horizontal_mask_right; + + /* 1 x N */ + if (x_steps == 1) { + if (y == y_steps-1) { + pp_inline_parameter->grf5.block_vertical_mask = pp_context->block_vertical_mask_bottom; + } + else { + pp_inline_parameter->grf6.block_vertical_mask_bottom = 0xff; + } + } + + /* M x 1 */ + if (y_steps == 1) { + if (x == 0) { // all blocks in this group are on the left edge + pp_inline_parameter->grf6.block_horizontal_mask_middle = pp_context->block_horizontal_mask_left; + pp_inline_parameter->grf6.block_horizontal_mask_right = pp_context->block_horizontal_mask_left; + } + else if (x == x_steps-1) { + pp_inline_parameter->grf5.block_horizontal_mask = pp_context->block_horizontal_mask_right; + pp_inline_parameter->grf6.block_horizontal_mask_middle = pp_context->block_horizontal_mask_right; + } + else { + pp_inline_parameter->grf5.block_horizontal_mask = 0xffff; + pp_inline_parameter->grf6.block_horizontal_mask_middle = 0xffff; + pp_inline_parameter->grf6.block_horizontal_mask_right = 0xffff; + } + } + +} + static void gen6_pp_object_walker(VADriverContextP ctx, struct i965_post_processing_context *pp_context) @@ -3330,6 +4166,10 @@ gen6_pp_object_walker(VADriverContextP ctx, for (y = 0; y < y_steps; y++) { for (x = 0; x < x_steps; x++) { if (!pp_context->pp_set_block_parameter(pp_context, x, y)) { + // some common block parameter update goes here, apply to all pp functions + if (IS_GEN6(i965->intel.device_id)) + update_block_mask_parameter (pp_context, x, y, x_steps, y_steps); + *command_ptr++ = (CMD_MEDIA_OBJECT | (command_length_in_dws - 2)); *command_ptr++ = 0; *command_ptr++ = 0; @@ -3449,6 +4289,23 @@ i965_CreateSurfaces(VADriverContextP ctx, int num_surfaces, VASurfaceID *surfaces); +static void +rgb_to_yuv(unsigned int argb, + unsigned char *y, + unsigned char *u, + unsigned char *v, + unsigned char *a) +{ + int r = ((argb >> 16) & 0xff); + int g = ((argb >> 8) & 0xff); + int b = ((argb >> 0) & 0xff); + + *y = (257 * r + 504 * g + 98 * b) / 1000 + 16; + *v = (439 * r - 368 * g - 71 * b) / 1000 + 128; + *u = (-148 * r - 291 * g + 439 * b) / 1000 + 128; + *a = ((argb >> 24) & 0xff); +} + static void i965_vpp_clear_surface(VADriverContextP ctx, struct i965_post_processing_context *pp_context, @@ -3461,11 +4318,17 @@ i965_vpp_clear_surface(VADriverContextP ctx, unsigned int blt_cmd, br13; unsigned int tiling = 0, swizzle = 0; int pitch; + unsigned char y, u, v, a = 0; /* Currently only support NV12 surface */ if (!obj_surface || obj_surface->fourcc != VA_FOURCC('N', 'V', '1', '2')) return; + rgb_to_yuv(color, &y, &u, &v, &a); + + if (a == 0) + return; + dri_bo_get_tiling(obj_surface->bo, &tiling, &swizzle); blt_cmd = XY_COLOR_BLT_CMD; pitch = obj_surface->width; @@ -3499,7 +4362,11 @@ i965_vpp_clear_surface(VADriverContextP ctx, OUT_RELOC(batch, obj_surface->bo, I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, 0); - OUT_BATCH(batch, 0x10); + OUT_BATCH(batch, y); + + br13 = 0xf0 << 16; + br13 |= BR13_565; + br13 |= pitch; OUT_BATCH(batch, blt_cmd); OUT_BATCH(batch, br13); @@ -3508,16 +4375,60 @@ i965_vpp_clear_surface(VADriverContextP ctx, 0); OUT_BATCH(batch, obj_surface->height / 2 << 16 | - obj_surface->width); + obj_surface->width / 2); OUT_RELOC(batch, obj_surface->bo, I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, obj_surface->width * obj_surface->y_cb_offset); - OUT_BATCH(batch, 0x80); + OUT_BATCH(batch, v << 8 | u); ADVANCE_BATCH(batch); intel_batchbuffer_end_atomic(batch); } +VAStatus +i965_scaling_processing( + VADriverContextP ctx, + VASurfaceID src_surface_id, + const VARectangle *src_rect, + VASurfaceID dst_surface_id, + const VARectangle *dst_rect, + unsigned int flags) +{ + VAStatus va_status = VA_STATUS_SUCCESS; + struct i965_driver_data *i965 = i965_driver_data(ctx); + struct object_surface *src_surface_obj = SURFACE(src_surface_id); + struct object_surface *dst_surface_obj = SURFACE(dst_surface_id); + + assert(src_surface_obj->fourcc == VA_FOURCC('N', 'V', '1', '2')); + assert(dst_surface_obj->fourcc == VA_FOURCC('N', 'V', '1', '2')); + + if (HAS_PP(i965) && (flags & I965_PP_FLAG_AVS)) { + struct i965_surface src_surface; + struct i965_surface dst_surface; + + _i965LockMutex(&i965->pp_mutex); + + src_surface.id = src_surface_id; + src_surface.type = I965_SURFACE_TYPE_SURFACE; + src_surface.flags = I965_SURFACE_FLAG_FRAME; + dst_surface.id = dst_surface_id; + dst_surface.type = I965_SURFACE_TYPE_SURFACE; + dst_surface.flags = I965_SURFACE_FLAG_FRAME; + + va_status = i965_post_processing_internal(ctx, i965->pp_context, + &src_surface, + src_rect, + &dst_surface, + dst_rect, + PP_NV12_AVS, + NULL); + + _i965UnlockMutex(&i965->pp_mutex); + } + + return va_status; +} + VASurfaceID i965_post_processing( VADriverContextP ctx, @@ -3548,7 +4459,7 @@ i965_post_processing( _i965LockMutex(&i965->pp_mutex); - if (flags & I965_PP_FLAG_DEINTERLACING) { + if (flags & I965_PP_FLAG_MCDI) { status = i965_CreateSurfaces(ctx, obj_surface->orig_width, obj_surface->orig_height, @@ -3561,7 +4472,7 @@ i965_post_processing( i965_vpp_clear_surface(ctx, i965->pp_context, out_surface_id, 0); src_surface.id = in_surface_id; src_surface.type = I965_SURFACE_TYPE_SURFACE; - src_surface.flags = (flags & I965_PP_FLAG_DEINTERLACING_TOP_FISRT) ? + src_surface.flags = (flags & I965_PP_FLAG_TOP_FIELD) ? I965_SURFACE_FLAG_TOP_FIELD_FIRST : I965_SURFACE_FLAG_BOTTOME_FIELD_FIRST; dst_surface.id = out_surface_id; dst_surface.type = I965_SURFACE_TYPE_SURFACE; @@ -3621,7 +4532,7 @@ i965_post_processing( } static VAStatus -i965_image_pl3_processing(VADriverContextP ctx, +i965_image_pl1_rgbx_processing(VADriverContextP ctx, const struct i965_surface *src_surface, const VARectangle *src_rect, struct i965_surface *dst_surface, @@ -3637,25 +4548,131 @@ i965_image_pl3_processing(VADriverContextP ctx, src_rect, dst_surface, dst_rect, - PP_PL3_LOAD_SAVE_N12, + PP_RGBX_LOAD_SAVE_NV12, NULL); } else { - i965_post_processing_internal(ctx, i965->pp_context, + assert(0); + return VA_STATUS_ERROR_UNKNOWN; + } + + intel_batchbuffer_flush(pp_context->batch); + + return VA_STATUS_SUCCESS; +} + +static VAStatus +i965_image_pl3_processing(VADriverContextP ctx, + const struct i965_surface *src_surface, + const VARectangle *src_rect, + struct i965_surface *dst_surface, + const VARectangle *dst_rect) +{ + struct i965_driver_data *i965 = i965_driver_data(ctx); + struct i965_post_processing_context *pp_context = i965->pp_context; + int fourcc = pp_get_surface_fourcc(ctx, dst_surface); + VAStatus vaStatus = VA_STATUS_ERROR_UNIMPLEMENTED; + + if (fourcc == VA_FOURCC('N', 'V', '1', '2')) { + vaStatus = i965_post_processing_internal(ctx, i965->pp_context, + src_surface, + src_rect, + dst_surface, + dst_rect, + PP_PL3_LOAD_SAVE_N12, + NULL); + } else if (fourcc == VA_FOURCC('I', 'M', 'C', '1') || + fourcc == VA_FOURCC('I', 'M', 'C', '3') || + fourcc == VA_FOURCC('Y', 'V', '1', '2') || + fourcc == VA_FOURCC('I', '4', '2', '0')) { + vaStatus = i965_post_processing_internal(ctx, i965->pp_context, + src_surface, + src_rect, + dst_surface, + dst_rect, + PP_PL3_LOAD_SAVE_PL3, + NULL); + } else if (fourcc == VA_FOURCC('Y', 'U', 'Y', '2') || + fourcc == VA_FOURCC('U', 'Y', 'V', 'Y')) { + vaStatus = i965_post_processing_internal(ctx, i965->pp_context, + src_surface, + src_rect, + dst_surface, + dst_rect, + PP_PL3_LOAD_SAVE_PA, + NULL); + } + else { + assert(0); + } + + intel_batchbuffer_flush(pp_context->batch); + + return vaStatus; +} + +static VAStatus +i965_image_pl2_processing(VADriverContextP ctx, + const struct i965_surface *src_surface, + const VARectangle *src_rect, + struct i965_surface *dst_surface, + const VARectangle *dst_rect) +{ + struct i965_driver_data *i965 = i965_driver_data(ctx); + struct i965_post_processing_context *pp_context = i965->pp_context; + int fourcc = pp_get_surface_fourcc(ctx, dst_surface); + VAStatus vaStatus = VA_STATUS_ERROR_UNIMPLEMENTED; + + if (fourcc == VA_FOURCC('N', 'V', '1', '2')) { + vaStatus = i965_post_processing_internal(ctx, i965->pp_context, + src_surface, + src_rect, + dst_surface, + dst_rect, + PP_NV12_LOAD_SAVE_N12, + NULL); + } else if (fourcc == VA_FOURCC('I', 'M', 'C', '1') || + fourcc == VA_FOURCC('I', 'M', 'C', '3') || + fourcc == VA_FOURCC('Y', 'V', '1', '2') || + fourcc == VA_FOURCC('I', '4', '2', '0') ) { + vaStatus = i965_post_processing_internal(ctx, i965->pp_context, + src_surface, + src_rect, + dst_surface, + dst_rect, + PP_NV12_LOAD_SAVE_PL3, + NULL); + } else if (fourcc == VA_FOURCC('Y', 'U', 'Y', '2') || + fourcc == VA_FOURCC('U', 'Y', 'V', 'Y')) { + vaStatus = i965_post_processing_internal(ctx, i965->pp_context, + src_surface, + src_rect, + dst_surface, + dst_rect, + PP_NV12_LOAD_SAVE_PA, + NULL); + } else if (fourcc == VA_FOURCC('B', 'G', 'R', 'X') || + fourcc == VA_FOURCC('B', 'G', 'R', 'A') || + fourcc == VA_FOURCC('R', 'G', 'B', 'X') || + fourcc == VA_FOURCC('R', 'G', 'B', 'A') ) { + vaStatus = i965_post_processing_internal(ctx, i965->pp_context, src_surface, src_rect, dst_surface, dst_rect, - PP_PL3_LOAD_SAVE_PL3, + PP_NV12_LOAD_SAVE_RGBX, NULL); + } else { + assert(0); + return VA_STATUS_ERROR_UNKNOWN; } intel_batchbuffer_flush(pp_context->batch); - return VA_STATUS_SUCCESS; + return vaStatus; } static VAStatus -i965_image_pl2_processing(VADriverContextP ctx, +i965_image_pl1_processing(VADriverContextP ctx, const struct i965_surface *src_surface, const VARectangle *src_rect, struct i965_surface *dst_surface, @@ -3671,16 +4688,21 @@ i965_image_pl2_processing(VADriverContextP ctx, src_rect, dst_surface, dst_rect, - PP_NV12_LOAD_SAVE_N12, + PP_PA_LOAD_SAVE_NV12, NULL); - } else { + } + else if (fourcc == VA_FOURCC_YV12) { i965_post_processing_internal(ctx, i965->pp_context, src_surface, src_rect, dst_surface, dst_rect, - PP_NV12_LOAD_SAVE_PL3, + PP_PA_LOAD_SAVE_PL3, NULL); + + } + else { + return VA_STATUS_ERROR_UNKNOWN; } intel_batchbuffer_flush(pp_context->batch); @@ -3722,7 +4744,24 @@ i965_image_processing(VADriverContextP ctx, dst_surface, dst_rect); break; - + case VA_FOURCC('Y', 'U', 'Y', '2'): + case VA_FOURCC('U', 'Y', 'V', 'Y'): + status = i965_image_pl1_processing(ctx, + src_surface, + src_rect, + dst_surface, + dst_rect); + break; + case VA_FOURCC('B', 'G', 'R', 'A'): + case VA_FOURCC('B', 'G', 'R', 'X'): + case VA_FOURCC('R', 'G', 'B', 'A'): + case VA_FOURCC('R', 'G', 'B', 'X'): + status = i965_image_pl1_rgbx_processing(ctx, + src_surface, + src_rect, + dst_surface, + dst_rect); + break; default: status = VA_STATUS_ERROR_UNIMPLEMENTED; break; @@ -3820,8 +4859,11 @@ i965_post_processing_context_init(VADriverContextP ctx, assert(NUM_PP_MODULES == ARRAY_ELEMS(pp_modules_gen5)); assert(NUM_PP_MODULES == ARRAY_ELEMS(pp_modules_gen6)); assert(NUM_PP_MODULES == ARRAY_ELEMS(pp_modules_gen7)); + assert(NUM_PP_MODULES == ARRAY_ELEMS(pp_modules_gen75)); - if (IS_GEN7(i965->intel.device_id)) + if (IS_HASWELL(i965->intel.device_id)) + memcpy(pp_context->pp_modules, pp_modules_gen75, sizeof(pp_context->pp_modules)); + else if (IS_GEN7(i965->intel.device_id)) memcpy(pp_context->pp_modules, pp_modules_gen7, sizeof(pp_context->pp_modules)); else if (IS_GEN6(i965->intel.device_id)) memcpy(pp_context->pp_modules, pp_modules_gen6, sizeof(pp_context->pp_modules)); @@ -3875,10 +4917,12 @@ i965_post_processing_init(VADriverContextP ctx) static const int procfilter_to_pp_flag[VAProcFilterCount] = { PP_NULL, /* VAProcFilterNone */ PP_NV12_DN, /* VAProcFilterNoiseReduction */ + PP_NULL, /* VAProcFilterDeblocking */ PP_NV12_DNDI, /* VAProcFilterDeinterlacing */ PP_NULL, /* VAProcFilterSharpening */ PP_NULL, /* VAProcFilterColorBalance */ PP_NULL, /* VAProcFilterColorStandard */ + PP_NULL, /* VAProcFilterFrameRateConversion */ }; static const int proc_frame_to_pp_frame[3] = { @@ -3887,7 +4931,7 @@ static const int proc_frame_to_pp_frame[3] = { I965_SURFACE_FLAG_BOTTOME_FIELD_FIRST }; -static void +void i965_proc_picture(VADriverContextP ctx, VAProfile profile, union codec_state *codec_state, @@ -3919,9 +4963,8 @@ i965_proc_picture(VADriverContextP ctx, src_surface.type = I965_SURFACE_TYPE_SURFACE; src_surface.flags = proc_frame_to_pp_frame[pipeline_param->filter_flags & 0x3]; + VASurfaceID out_surface_id = VA_INVALID_ID; if (obj_surface->fourcc != VA_FOURCC('N', 'V', '1', '2')) { - VASurfaceID out_surface_id = VA_INVALID_ID; - src_surface.id = pipeline_param->surface; src_surface.type = I965_SURFACE_TYPE_SURFACE; src_surface.flags = I965_SURFACE_FLAG_FRAME; @@ -3985,16 +5028,15 @@ i965_proc_picture(VADriverContextP ctx, dst_rect.height = in_height; } - obj_surface = SURFACE(proc_state->current_render_target); - i965_check_alloc_surface_bo(ctx, obj_surface, !!tiling, VA_FOURCC('N','V','1','2'), SUBSAMPLE_YUV420); - for (i = 0; i < pipeline_param->num_filters; i++) { struct object_buffer *obj_buffer = BUFFER(pipeline_param->filters[i]); VAProcFilterParameterBufferBase *filter_param = (VAProcFilterParameterBufferBase *)obj_buffer->buffer_store->buffer; VAProcFilterType filter_type = filter_param->type; - VASurfaceID out_surface_id = VA_INVALID_ID; + out_surface_id = VA_INVALID_ID; + int kernel_index = procfilter_to_pp_flag[filter_type]; - if (procfilter_to_pp_flag[filter_type] != PP_NULL) { + if (kernel_index != PP_NULL && + proc_context->pp_context.pp_modules[kernel_index].kernel.bo != NULL) { status = i965_CreateSurfaces(ctx, in_width, in_height, @@ -4012,7 +5054,7 @@ i965_proc_picture(VADriverContextP ctx, &src_rect, &dst_surface, &src_rect, - procfilter_to_pp_flag[filter_type], + kernel_index, filter_param); if (status == VA_STATUS_SUCCESS) { @@ -4023,17 +5065,63 @@ i965_proc_picture(VADriverContextP ctx, } } - dst_surface.id = proc_state->current_render_target; + obj_surface = SURFACE(proc_state->current_render_target); + int csc_needed = 0; + if (obj_surface->fourcc && obj_surface->fourcc != VA_FOURCC('N','V','1','2')){ + csc_needed = 1; + out_surface_id = VA_INVALID_ID; + status = i965_CreateSurfaces(ctx, + obj_surface->orig_width, + obj_surface->orig_height, + VA_RT_FORMAT_YUV420, + 1, + &out_surface_id); + assert(status == VA_STATUS_SUCCESS); + tmp_surfaces[num_tmp_surfaces++] = out_surface_id; + struct object_surface *csc_surface = SURFACE(out_surface_id); + i965_check_alloc_surface_bo(ctx, csc_surface, !!tiling, VA_FOURCC('N','V','1','2'), SUBSAMPLE_YUV420); + dst_surface.id = out_surface_id; + } else { + i965_check_alloc_surface_bo(ctx, obj_surface, !!tiling, VA_FOURCC('N','V','1','2'), SUBSAMPLE_YUV420); + dst_surface.id = proc_state->current_render_target; + } + dst_surface.type = I965_SURFACE_TYPE_SURFACE; - i965_post_processing_internal(ctx, &proc_context->pp_context, - &src_surface, - &src_rect, - &dst_surface, - &dst_rect, - (pipeline_param->filter_flags & VA_FILTER_SCALING_MASK) == VA_FILTER_SCALING_NL_ANAMORPHIC ? - PP_NV12_AVS : PP_NV12_SCALING, - NULL); + i965_vpp_clear_surface(ctx, &proc_context->pp_context, proc_state->current_render_target, pipeline_param->output_background_color); + + // load/save doesn't support different origin offset for src and dst surface + if (src_rect.width == dst_rect.width && + src_rect.height == dst_rect.height && + src_rect.x == dst_rect.x && + src_rect.y == dst_rect.y) { + i965_post_processing_internal(ctx, &proc_context->pp_context, + &src_surface, + &src_rect, + &dst_surface, + &dst_rect, + PP_NV12_LOAD_SAVE_N12, + NULL); + } else { + + i965_post_processing_internal(ctx, &proc_context->pp_context, + &src_surface, + &src_rect, + &dst_surface, + &dst_rect, + (pipeline_param->filter_flags & VA_FILTER_SCALING_MASK) == VA_FILTER_SCALING_NL_ANAMORPHIC ? + PP_NV12_AVS : PP_NV12_SCALING, + NULL); + } + if (csc_needed) { + src_surface.id = dst_surface.id; + src_surface.type = dst_surface.type; + src_surface.flags = dst_surface.flags; + dst_surface.id = proc_state->current_render_target; + dst_surface.type = I965_SURFACE_TYPE_SURFACE; + i965_image_processing(ctx, &src_surface, &dst_rect, &dst_surface, &dst_rect); + } + if (num_tmp_surfaces) i965_DestroySurfaces(ctx, tmp_surfaces, @@ -4060,7 +5148,7 @@ i965_proc_context_init(VADriverContextP ctx, struct object_config *obj_config) proc_context->base.destroy = i965_proc_context_destroy; proc_context->base.run = i965_proc_picture; - proc_context->base.batch = intel_batchbuffer_new(intel, I915_EXEC_RENDER); + proc_context->base.batch = intel_batchbuffer_new(intel, I915_EXEC_RENDER, 0); i965_post_processing_context_init(ctx, &proc_context->pp_context, proc_context->base.batch); return (struct hw_context *)proc_context;