X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=src%2Fgallium%2Fdrivers%2Fr600%2Fr600_pipe.h;h=ba75c9d5c1cfa71719117a3c7cfc6eb68f6da9cb;hb=78222e63630280b96488de0d51d1b2578e26f814;hp=d92de427ef80b315b5716e357dd19f3e0ef1feba;hpb=6ed5855009a0ab8c6f88cad1ae517e49d8953d98;p=profile%2Fivi%2Fmesa.git diff --git a/src/gallium/drivers/r600/r600_pipe.h b/src/gallium/drivers/r600/r600_pipe.h index d92de42..ba75c9d 100644 --- a/src/gallium/drivers/r600/r600_pipe.h +++ b/src/gallium/drivers/r600/r600_pipe.h @@ -26,18 +26,14 @@ #ifndef R600_PIPE_H #define R600_PIPE_H -#include "../../winsys/radeon/drm/radeon_winsys.h" - -#include "pipe/p_state.h" -#include "pipe/p_screen.h" -#include "pipe/p_context.h" -#include "util/u_math.h" +#include "util/u_blitter.h" #include "util/u_slab.h" -#include "util/u_vbuf.h" #include "r600.h" +#include "r600_llvm.h" #include "r600_public.h" #include "r600_shader.h" #include "r600_resource.h" +#include "evergreen_compute.h" #define R600_MAX_CONST_BUFFERS 2 #define R600_MAX_CONST_BUFFER_SIZE 4096 @@ -73,23 +69,49 @@ struct r600_command_buffer { struct r600_atom atom; uint32_t *buf; unsigned max_num_dw; + unsigned pkt_flags; }; -struct r600_atom_surface_sync { +struct r600_surface_sync_cmd { struct r600_atom atom; unsigned flush_flags; /* CP_COHER_CNTL */ }; -struct r600_atom_db_misc_state { +struct r600_db_misc_state { struct r600_atom atom; bool occlusion_query_enabled; - bool flush_depthstencil_enabled; + bool flush_depthstencil_through_cb; + bool copy_depth, copy_stencil; + unsigned copy_sample; + unsigned log_samples; +}; + +struct r600_cb_misc_state { + struct r600_atom atom; + unsigned cb_color_control; /* this comes from blend state */ + unsigned blend_colormask; /* 8*4 bits for 8 RGBA colorbuffers */ + unsigned nr_cbufs; + unsigned nr_ps_color_outputs; + bool multiwrite; + bool dual_src_blend; }; -struct r600_atom_eg_strmout_config { +struct r600_alphatest_state { struct r600_atom atom; - bool rasterizer_discard; - bool stream0_enable; + unsigned sx_alpha_test_control; /* this comes from dsa state */ + unsigned sx_alpha_ref; /* this comes from dsa state */ + bool bypass; + bool cb0_export_16bpc; /* from set_framebuffer_state */ +}; + +struct r600_cs_shader_state { + struct r600_atom atom; + struct r600_pipe_compute *shader; +}; + +struct r600_sample_mask { + struct r600_atom atom; + uint16_t sample_mask; /* there are only 8 bits on EG, 16 bits on Cayman */ }; enum r600_pipe_state_id { @@ -112,9 +134,15 @@ enum r600_pipe_state_id { R600_PIPE_STATE_RESOURCE, R600_PIPE_STATE_POLYGON_OFFSET, R600_PIPE_STATE_FETCH_SHADER, + R600_PIPE_STATE_SPI, R600_PIPE_NSTATES }; +struct compute_memory_pool; +void compute_memory_pool_delete(struct compute_memory_pool* pool); +struct compute_memory_pool* compute_memory_pool_new( + struct r600_screen *rscreen); + struct r600_pipe_fences { struct r600_resource *bo; unsigned *data; @@ -132,20 +160,21 @@ struct r600_screen { unsigned family; enum chip_class chip_class; struct radeon_info info; + bool has_streamout; struct r600_tiling_info tiling_info; - struct util_slab_mempool pool_buffers; struct r600_pipe_fences fences; - unsigned num_contexts; - bool use_surface_alloc; - - /* for thread-safe write accessing to num_contexts */ - pipe_mutex mutex_num_contexts; + /*for compute global memory binding, we allocate stuff here, instead of + * buffers. + * XXX: Not sure if this is the best place for global_pool. Also, + * it's not thread safe, so it won't work with multiple contexts. */ + struct compute_memory_pool *global_pool; }; struct r600_pipe_sampler_view { struct pipe_sampler_view base; - struct r600_pipe_resource_state state; + struct r600_resource *tex_resource; + uint32_t tex_resource_words[8]; }; struct r600_pipe_rasterizer { @@ -159,13 +188,15 @@ struct r600_pipe_rasterizer { float offset_units; float offset_scale; bool scissor_enable; - bool rasterizer_discard; + bool multisample_enable; }; struct r600_pipe_blend { struct r600_pipe_state rstate; unsigned cb_target_mask; unsigned cb_color_control; + bool dual_src_blend; + bool alpha_to_one; }; struct r600_pipe_dsa { @@ -173,58 +204,87 @@ struct r600_pipe_dsa { unsigned alpha_ref; ubyte valuemask[2]; ubyte writemask[2]; - bool is_flush; + unsigned sx_alpha_test_control; }; struct r600_vertex_element { unsigned count; struct pipe_vertex_element elements[PIPE_MAX_ATTRIBS]; - struct u_vbuf_elements *vmgr_elements; struct r600_resource *fetch_shader; unsigned fs_size; struct r600_pipe_state rstate; - /* if offset is to big for fetch instructio we need to alterate - * offset of vertex buffer, record here the offset need to add - */ - unsigned vbuffer_need_offset; - unsigned vbuffer_offset[PIPE_MAX_ATTRIBS]; +}; + +struct r600_pipe_shader; + +struct r600_pipe_shader_selector { + struct r600_pipe_shader *current; + + struct tgsi_token *tokens; + struct pipe_stream_output_info so; + + unsigned num_shaders; + + /* PIPE_SHADER_[VERTEX|FRAGMENT|...] */ + unsigned type; + + unsigned nr_ps_max_color_exports; }; struct r600_pipe_shader { + struct r600_pipe_shader_selector *selector; + struct r600_pipe_shader *next_variant; struct r600_shader shader; struct r600_pipe_state rstate; struct r600_resource *bo; struct r600_resource *bo_fetch; struct r600_vertex_element vertex_elements; - struct tgsi_token *tokens; unsigned sprite_coord_enable; unsigned flatshade; unsigned pa_cl_vs_out_cntl; - struct pipe_stream_output_info so; + unsigned nr_ps_color_outputs; + unsigned key; + unsigned db_shader_control; + unsigned ps_depth_export; }; struct r600_pipe_sampler_state { - struct r600_pipe_state rstate; - boolean seamless_cube_map; + uint32_t tex_sampler_words[3]; + uint32_t border_color[4]; + bool border_color_use; + bool seamless_cube_map; }; /* needed for blitter save */ #define NUM_TEX_UNITS 16 -struct r600_textures_info { +struct r600_seamless_cube_map { + struct r600_atom atom; + bool enabled; +}; + +struct r600_samplerview_state { + struct r600_atom atom; struct r600_pipe_sampler_view *views[NUM_TEX_UNITS]; + uint32_t enabled_mask; + uint32_t dirty_mask; + uint32_t compressed_depthtex_mask; /* which textures are depth */ + uint32_t compressed_colortex_mask; +}; + +struct r600_textures_info { + struct r600_samplerview_state views; + struct r600_atom atom_sampler; struct r600_pipe_sampler_state *samplers[NUM_TEX_UNITS]; - unsigned n_views; unsigned n_samplers; - bool samplers_dirty; bool is_array_sampler[NUM_TEX_UNITS]; }; struct r600_fence { struct pipe_reference reference; unsigned index; /* in the shared bo */ - struct r600_resource *sleep_bo; + struct r600_resource *sleep_bo; struct list_head head; }; @@ -245,33 +305,49 @@ struct r600_stencil_ref ubyte writemask[2]; }; +struct r600_constbuf_state +{ + struct r600_atom atom; + struct pipe_constant_buffer cb[PIPE_MAX_CONSTANT_BUFFERS]; + uint32_t enabled_mask; + uint32_t dirty_mask; +}; + +struct r600_vertexbuf_state +{ + struct r600_atom atom; + struct pipe_vertex_buffer vb[PIPE_MAX_ATTRIBS]; + uint32_t enabled_mask; /* non-NULL buffers */ + uint32_t dirty_mask; +}; + struct r600_context { struct pipe_context context; struct blitter_context *blitter; enum radeon_family family; enum chip_class chip_class; + boolean has_vertex_cache; unsigned r6xx_num_clause_temp_gprs; void *custom_dsa_flush; + void *custom_blend_resolve; + void *custom_blend_decompress; + struct r600_screen *screen; struct radeon_winsys *ws; struct r600_pipe_state *states[R600_PIPE_NSTATES]; struct r600_vertex_element *vertex_elements; - struct r600_pipe_resource_state fs_resource[PIPE_MAX_ATTRIBS]; struct pipe_framebuffer_state framebuffer; - unsigned cb_target_mask; - unsigned cb_color_control; + unsigned compressed_cb_mask; + unsigned compute_cb_target_mask; + unsigned db_shader_control; unsigned pa_sc_line_stipple; unsigned pa_cl_clip_cntl; /* for saving when using blitter */ struct pipe_stencil_ref stencil_ref; struct pipe_viewport_state viewport; struct pipe_clip_state clip; - struct r600_pipe_shader *ps_shader; - struct r600_pipe_shader *vs_shader; - struct r600_pipe_state vs_const_buffer; - struct r600_pipe_resource_state vs_const_buffer_resource[R600_MAX_CONST_BUFFERS]; - struct r600_pipe_state ps_const_buffer; - struct r600_pipe_resource_state ps_const_buffer_resource[R600_MAX_CONST_BUFFERS]; + struct r600_pipe_shader_selector *ps_shader; + struct r600_pipe_shader_selector *vs_shader; struct r600_pipe_rasterizer *rasterizer; struct r600_pipe_state vgt; struct r600_pipe_state spi; @@ -281,37 +357,61 @@ struct r600_context { unsigned saved_render_cond_mode; /* shader information */ boolean two_side; + boolean spi_dirty; unsigned sprite_coord_enable; + boolean flatshade; boolean export_16bpc; - unsigned alpha_ref; - boolean alpha_ref_dirty; unsigned nr_cbufs; - struct r600_textures_info vs_samplers; - struct r600_textures_info ps_samplers; + bool alpha_to_one; + bool multisample_enable; + bool cb0_is_integer; - struct u_vbuf *vbuf_mgr; + struct u_upload_mgr *uploader; struct util_slab_mempool pool_transfers; - boolean have_depth_texture, have_depth_fb; unsigned default_ps_gprs, default_vs_gprs; - /* States based on r600_state. */ + /* current unaccounted memory usage */ + uint64_t vram; + uint64_t gtt; + + /* States based on r600_atom. */ struct list_head dirty_states; - struct r600_command_buffer atom_start_cs; /* invariant state mostly */ - struct r600_atom_surface_sync atom_surface_sync; - struct r600_atom atom_r6xx_flush_and_inv; - struct r600_atom_db_misc_state atom_db_misc_state; - struct r600_atom_eg_strmout_config atom_eg_strmout_config; + struct r600_command_buffer start_cs_cmd; /* invariant state mostly */ + /** Compute specific registers initializations. The start_cs_cmd atom + * must be emitted before start_compute_cs_cmd. */ + struct r600_command_buffer start_compute_cs_cmd; + struct r600_surface_sync_cmd surface_sync_cmd; + struct r600_atom r6xx_flush_and_inv_cmd; + struct r600_alphatest_state alphatest_state; + struct r600_cb_misc_state cb_misc_state; + struct r600_db_misc_state db_misc_state; + /** Vertex buffers for fetch shaders */ + struct r600_vertexbuf_state vertex_buffer_state; + /** Vertex buffers for compute shaders */ + struct r600_vertexbuf_state cs_vertex_buffer_state; + struct r600_constbuf_state vs_constbuf_state; + struct r600_constbuf_state ps_constbuf_state; + struct r600_textures_info vs_samplers; + struct r600_textures_info ps_samplers; + struct r600_seamless_cube_map seamless_cube_map; + struct r600_cs_shader_state cs_shader_state; + struct r600_sample_mask sample_mask; + + /* current external blend state (from state tracker) */ + struct r600_pipe_blend *blend; + /* state with disabled blending - used internally with blend_override */ + struct r600_pipe_blend *no_blend; + + /* 1 - override current blend state with no_blend, 0 - use external state */ + unsigned blend_override; - /* Below are variables from the old r600_context. - */ struct radeon_winsys_cs *cs; struct r600_range *range; unsigned nblocks; struct r600_block **blocks; struct list_head dirty; - struct list_head resource_dirty; struct list_head enable_list; unsigned pm4_dirty_cdwords; unsigned ctx_pm4_ndwords; @@ -336,10 +436,6 @@ struct r600_context { unsigned max_db; /* for OQ */ unsigned flags; boolean predicate_drawing; - struct r600_range ps_resources; - struct r600_range vs_resources; - struct r600_range fs_resources; - int num_ps_resources, num_vs_resources, num_fs_resources; unsigned num_so_targets; struct r600_so_target *so_targets[PIPE_MAX_SO_BUFFERS]; @@ -354,6 +450,18 @@ struct r600_context { /* With rasterizer discard, there doesn't have to be a pixel shader. * In that case, we bind this one: */ void *dummy_pixel_shader; + + boolean dual_src_blend; + + /* Index buffer. */ + struct pipe_index_buffer index_buffer; + + /* Dummy CMASK and FMASK buffers used to get around the R6xx hardware + * bug where valid CMASK and FMASK are required to be present to avoid + * a hardlock in certain operations but aren't actually used + * for anything useful. */ + struct r600_resource *dummy_fmask; + struct r600_resource *dummy_cmask; }; static INLINE void r600_emit_atom(struct r600_context *rctx, struct r600_atom *atom) @@ -377,32 +485,44 @@ static INLINE void r600_atom_dirty(struct r600_context *rctx, struct r600_atom * } /* evergreen_state.c */ +void evergreen_init_common_regs(struct r600_command_buffer *cb, + enum chip_class ctx_chip_class, + enum radeon_family ctx_family, + int ctx_drm_minor); + void evergreen_init_state_functions(struct r600_context *rctx); void evergreen_init_atom_start_cs(struct r600_context *rctx); void evergreen_pipe_shader_ps(struct pipe_context *ctx, struct r600_pipe_shader *shader); void evergreen_pipe_shader_vs(struct pipe_context *ctx, struct r600_pipe_shader *shader); void evergreen_fetch_shader(struct pipe_context *ctx, struct r600_vertex_element *ve); void *evergreen_create_db_flush_dsa(struct r600_context *rctx); +void *evergreen_create_resolve_blend(struct r600_context *rctx); +void *evergreen_create_decompress_blend(struct r600_context *rctx); void evergreen_polygon_offset_update(struct r600_context *rctx); -void evergreen_pipe_init_buffer_resource(struct r600_context *rctx, - struct r600_pipe_resource_state *rstate); -void evergreen_pipe_mod_buffer_resource(struct pipe_context *ctx, - struct r600_pipe_resource_state *rstate, - struct r600_resource *rbuffer, - unsigned offset, unsigned stride, - enum radeon_bo_usage usage); boolean evergreen_is_format_supported(struct pipe_screen *screen, enum pipe_format format, enum pipe_texture_target target, unsigned sample_count, unsigned usage); -void evergreen_set_rasterizer_discard(struct pipe_context *ctx, boolean discard); +void evergreen_init_color_surface(struct r600_context *rctx, + struct r600_surface *surf); +void evergreen_update_dual_export_state(struct r600_context * rctx); /* r600_blit.c */ +void r600_copy_buffer(struct pipe_context *ctx, struct + pipe_resource *dst, unsigned dstx, + struct pipe_resource *src, const struct pipe_box *src_box); void r600_init_blit_functions(struct r600_context *rctx); -void r600_blit_uncompress_depth(struct pipe_context *ctx, struct r600_resource_texture *texture); -void r600_blit_push_depth(struct pipe_context *ctx, struct r600_resource_texture *texture); -void r600_flush_depth_textures(struct r600_context *rctx); +void r600_blit_decompress_depth(struct pipe_context *ctx, + struct r600_texture *texture, + struct r600_texture *staging, + unsigned first_level, unsigned last_level, + unsigned first_layer, unsigned last_layer, + unsigned first_sample, unsigned last_sample); +void r600_decompress_depth_textures(struct r600_context *rctx, + struct r600_samplerview_state *textures); +void r600_decompress_color_textures(struct r600_context *rctx, + struct r600_samplerview_state *textures); /* r600_buffer.c */ bool r600_init_resource(struct r600_screen *rscreen, @@ -410,13 +530,8 @@ bool r600_init_resource(struct r600_screen *rscreen, unsigned size, unsigned alignment, unsigned bind, unsigned usage); struct pipe_resource *r600_buffer_create(struct pipe_screen *screen, - const struct pipe_resource *templ); -struct pipe_resource *r600_user_buffer_create(struct pipe_screen *screen, - void *ptr, unsigned bytes, - unsigned bind); -void r600_upload_index_buffer(struct r600_context *rctx, - struct pipe_index_buffer *ib, unsigned count); - + const struct pipe_resource *templ, + unsigned alignment); /* r600_pipe.c */ void r600_flush(struct pipe_context *ctx, struct pipe_fence_handle **fence, @@ -434,33 +549,32 @@ void r600_init_context_resource_functions(struct r600_context *r600); /* r600_shader.c */ int r600_pipe_shader_create(struct pipe_context *ctx, struct r600_pipe_shader *shader); +#ifdef HAVE_OPENCL +int r600_compute_shader_create(struct pipe_context * ctx, + LLVMModuleRef mod, struct r600_bytecode * bytecode); +#endif void r600_pipe_shader_destroy(struct pipe_context *ctx, struct r600_pipe_shader *shader); -int r600_find_vs_semantic_index(struct r600_shader *vs, - struct r600_shader *ps, int id); /* r600_state.c */ void r600_set_scissor_state(struct r600_context *rctx, const struct pipe_scissor_state *state); -void r600_update_sampler_states(struct r600_context *rctx); void r600_init_state_functions(struct r600_context *rctx); void r600_init_atom_start_cs(struct r600_context *rctx); void r600_pipe_shader_ps(struct pipe_context *ctx, struct r600_pipe_shader *shader); void r600_pipe_shader_vs(struct pipe_context *ctx, struct r600_pipe_shader *shader); void r600_fetch_shader(struct pipe_context *ctx, struct r600_vertex_element *ve); void *r600_create_db_flush_dsa(struct r600_context *rctx); +void *r600_create_resolve_blend(struct r600_context *rctx); +void *r700_create_resolve_blend(struct r600_context *rctx); +void *r600_create_decompress_blend(struct r600_context *rctx); void r600_polygon_offset_update(struct r600_context *rctx); -void r600_pipe_init_buffer_resource(struct r600_context *rctx, - struct r600_pipe_resource_state *rstate); -void r600_pipe_mod_buffer_resource(struct r600_pipe_resource_state *rstate, - struct r600_resource *rbuffer, - unsigned offset, unsigned stride, - enum radeon_bo_usage usage); void r600_adjust_gprs(struct r600_context *rctx); boolean r600_is_format_supported(struct pipe_screen *screen, enum pipe_format format, enum pipe_texture_target target, unsigned sample_count, unsigned usage); +void r600_update_dual_export_state(struct r600_context * rctx); /* r600_texture.c */ void r600_init_screen_texture_functions(struct pipe_screen *screen); @@ -468,7 +582,7 @@ void r600_init_surface_functions(struct r600_context *r600); uint32_t r600_translate_texformat(struct pipe_screen *screen, enum pipe_format format, const unsigned char *swizzle_view, uint32_t *word4_p, uint32_t *yuv_format_p); -unsigned r600_texture_get_offset(struct r600_resource_texture *rtex, +unsigned r600_texture_get_offset(struct r600_texture *rtex, unsigned level, unsigned layer); /* r600_translate.c */ @@ -485,8 +599,18 @@ unsigned r600_get_cb_flush_flags(struct r600_context *rctx); void r600_texture_barrier(struct pipe_context *ctx); void r600_set_index_buffer(struct pipe_context *ctx, const struct pipe_index_buffer *ib); +void r600_vertex_buffers_dirty(struct r600_context *rctx); void r600_set_vertex_buffers(struct pipe_context *ctx, unsigned count, - const struct pipe_vertex_buffer *buffers); + const struct pipe_vertex_buffer *input); +void r600_sampler_views_dirty(struct r600_context *rctx, + struct r600_samplerview_state *state); +void r600_set_sampler_views(struct pipe_context *pipe, + unsigned shader, + unsigned start, + unsigned count, + struct pipe_sampler_view **views); +void r600_bind_vs_samplers(struct pipe_context *ctx, unsigned count, void **states); +void r600_bind_ps_samplers(struct pipe_context *ctx, unsigned count, void **states); void *r600_create_vertex_elements(struct pipe_context *ctx, unsigned count, const struct pipe_vertex_element *elements); @@ -500,16 +624,20 @@ void r600_bind_rs_state(struct pipe_context *ctx, void *state); void r600_delete_rs_state(struct pipe_context *ctx, void *state); void r600_sampler_view_destroy(struct pipe_context *ctx, struct pipe_sampler_view *state); +void r600_delete_sampler(struct pipe_context *ctx, void *state); void r600_delete_state(struct pipe_context *ctx, void *state); void r600_bind_vertex_elements(struct pipe_context *ctx, void *state); -void *r600_create_shader_state(struct pipe_context *ctx, - const struct pipe_shader_state *state); +void *r600_create_shader_state_ps(struct pipe_context *ctx, + const struct pipe_shader_state *state); +void *r600_create_shader_state_vs(struct pipe_context *ctx, + const struct pipe_shader_state *state); void r600_bind_ps_shader(struct pipe_context *ctx, void *state); void r600_bind_vs_shader(struct pipe_context *ctx, void *state); void r600_delete_ps_shader(struct pipe_context *ctx, void *state); void r600_delete_vs_shader(struct pipe_context *ctx, void *state); +void r600_constant_buffers_dirty(struct r600_context *rctx, struct r600_constbuf_state *state); void r600_set_constant_buffer(struct pipe_context *ctx, uint shader, uint index, - struct pipe_resource *buffer); + struct pipe_constant_buffer *cb); struct pipe_stream_output_target * r600_create_so_target(struct pipe_context *ctx, struct pipe_resource *buffer, @@ -521,9 +649,13 @@ void r600_set_so_targets(struct pipe_context *ctx, unsigned num_targets, struct pipe_stream_output_target **targets, unsigned append_bitmask); +void r600_set_sample_mask(struct pipe_context *pipe, unsigned sample_mask); void r600_set_pipe_stencil_ref(struct pipe_context *ctx, const struct pipe_stencil_ref *state); void r600_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info); +void r600_draw_rectangle(struct blitter_context *blitter, + unsigned x1, unsigned y1, unsigned x2, unsigned y2, float depth, + enum blitter_attrib_type type, const union pipe_color_union *attrib); uint32_t r600_translate_stencil_op(int s_op); uint32_t r600_translate_fill(uint32_t func); unsigned r600_tex_wrap(unsigned wrap); @@ -552,6 +684,11 @@ unsigned r600_tex_compare(unsigned compare); #define PKT3_PREDICATE(x) (((x) >> 0) & 0x1) #define PKT3(op, count, predicate) (PKT_TYPE_S(3) | PKT_COUNT_S(count) | PKT3_IT_OPCODE_S(op) | PKT3_PREDICATE(predicate)) +#define RADEON_CP_PACKET3_COMPUTE_MODE 0x00000002 + +/*Evergreen Compute packet3*/ +#define PKT3C(op, count, predicate) (PKT_TYPE_S(3) | PKT3_IT_OPCODE_S(op) | PKT_COUNT_S(count) | PKT3_PREDICATE(predicate) | RADEON_CP_PACKET3_COMPUTE_MODE) + static INLINE void r600_store_value(struct r600_command_buffer *cb, unsigned value) { cb->buf[cb->atom.num_dw++] = value; @@ -565,19 +702,27 @@ static INLINE void r600_store_config_reg_seq(struct r600_command_buffer *cb, uns cb->buf[cb->atom.num_dw++] = (reg - R600_CONFIG_REG_OFFSET) >> 2; } +/** + * Needs cb->pkt_flags set to RADEON_CP_PACKET3_COMPUTE_MODE for compute + * shaders. + */ static INLINE void r600_store_context_reg_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num) { assert(reg >= R600_CONTEXT_REG_OFFSET && reg < R600_CTL_CONST_OFFSET); assert(cb->atom.num_dw+2+num <= cb->max_num_dw); - cb->buf[cb->atom.num_dw++] = PKT3(PKT3_SET_CONTEXT_REG, num, 0); + cb->buf[cb->atom.num_dw++] = PKT3(PKT3_SET_CONTEXT_REG, num, 0) | cb->pkt_flags; cb->buf[cb->atom.num_dw++] = (reg - R600_CONTEXT_REG_OFFSET) >> 2; } +/** + * Needs cb->pkt_flags set to RADEON_CP_PACKET3_COMPUTE_MODE for compute + * shaders. + */ static INLINE void r600_store_ctl_const_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num) { assert(reg >= R600_CTL_CONST_OFFSET); assert(cb->atom.num_dw+2+num <= cb->max_num_dw); - cb->buf[cb->atom.num_dw++] = PKT3(PKT3_SET_CTL_CONST, num, 0); + cb->buf[cb->atom.num_dw++] = PKT3(PKT3_SET_CTL_CONST, num, 0) | cb->pkt_flags; cb->buf[cb->atom.num_dw++] = (reg - R600_CTL_CONST_OFFSET) >> 2; } @@ -589,11 +734,15 @@ static INLINE void r600_store_loop_const_seq(struct r600_command_buffer *cb, uns cb->buf[cb->atom.num_dw++] = (reg - R600_LOOP_CONST_OFFSET) >> 2; } +/** + * Needs cb->pkt_flags set to RADEON_CP_PACKET3_COMPUTE_MODE for compute + * shaders. + */ static INLINE void eg_store_loop_const_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num) { assert(reg >= EG_LOOP_CONST_OFFSET); assert(cb->atom.num_dw+2+num <= cb->max_num_dw); - cb->buf[cb->atom.num_dw++] = PKT3(PKT3_SET_LOOP_CONST, num, 0); + cb->buf[cb->atom.num_dw++] = PKT3(PKT3_SET_LOOP_CONST, num, 0) | cb->pkt_flags; cb->buf[cb->atom.num_dw++] = (reg - EG_LOOP_CONST_OFFSET) >> 2; } @@ -646,6 +795,13 @@ static INLINE void r600_write_value(struct radeon_winsys_cs *cs, unsigned value) cs->buf[cs->cdw++] = value; } +static INLINE void r600_write_array(struct radeon_winsys_cs *cs, unsigned num, unsigned *ptr) +{ + assert(cs->cdw+num <= RADEON_MAX_CMDBUF_DWORDS); + memcpy(&cs->buf[cs->cdw], ptr, num * sizeof(ptr[0])); + cs->cdw += num; +} + static INLINE void r600_write_config_reg_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num) { assert(reg < R600_CONTEXT_REG_OFFSET); @@ -662,6 +818,13 @@ static INLINE void r600_write_context_reg_seq(struct radeon_winsys_cs *cs, unsig cs->buf[cs->cdw++] = (reg - R600_CONTEXT_REG_OFFSET) >> 2; } +static INLINE void r600_write_compute_context_reg_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num) +{ + r600_write_context_reg_seq(cs, reg, num); + /* Set the compute bit on the packet header */ + cs->buf[cs->cdw - 2] |= RADEON_CP_PACKET3_COMPUTE_MODE; +} + static INLINE void r600_write_ctl_const_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num) { assert(reg >= R600_CTL_CONST_OFFSET); @@ -682,6 +845,12 @@ static INLINE void r600_write_context_reg(struct radeon_winsys_cs *cs, unsigned r600_write_value(cs, value); } +static INLINE void r600_write_compute_context_reg(struct radeon_winsys_cs *cs, unsigned reg, unsigned value) +{ + r600_write_compute_context_reg_seq(cs, reg, 1); + r600_write_value(cs, value); +} + static INLINE void r600_write_ctl_const(struct radeon_winsys_cs *cs, unsigned reg, unsigned value) { r600_write_ctl_const_seq(cs, reg, 1); @@ -713,4 +882,36 @@ static INLINE unsigned r600_pack_float_12p4(float x) x >= 4096 ? 0xffff : x * 16; } +static INLINE uint64_t r600_resource_va(struct pipe_screen *screen, struct pipe_resource *resource) +{ + struct r600_screen *rscreen = (struct r600_screen*)screen; + struct r600_resource *rresource = (struct r600_resource*)resource; + + return rscreen->ws->buffer_get_virtual_address(rresource->cs_buf); +} + +static INLINE void r600_context_add_resource_size(struct pipe_context *ctx, struct pipe_resource *r) +{ + struct r600_context *rctx = (struct r600_context *)ctx; + struct r600_resource *rr = (struct r600_resource *)r; + + if (r == NULL) { + return; + } + + /* + * The idea is to compute a gross estimate of memory requirement of + * each draw call. After each draw call, memory will be precisely + * accounted. So the uncertainty is only on the current draw call. + * In practice this gave very good estimate (+/- 10% of the target + * memory limit). + */ + if (rr->domains & RADEON_DOMAIN_GTT) { + rctx->gtt += rr->buf->size; + } + if (rr->domains & RADEON_DOMAIN_VRAM) { + rctx->vram += rr->buf->size; + } +} + #endif