X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=post%2Fcpu%2Fppc4xx%2Fether.c;h=8a4c56b7d622ead7495710294a3a64b69a88b352;hb=da684a646d0c94f7a6126e7ecf110278691465a6;hp=ab23ca5a3dbc6f420d41ad9204bfce6dd428959c;hpb=34886bbea20b577e8bdef81f3831319f1876b9b7;p=platform%2Fkernel%2Fu-boot.git diff --git a/post/cpu/ppc4xx/ether.c b/post/cpu/ppc4xx/ether.c index ab23ca5..8a4c56b 100644 --- a/post/cpu/ppc4xx/ether.c +++ b/post/cpu/ppc4xx/ether.c @@ -4,23 +4,7 @@ * * Author: Igor Lisitsin * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA + * SPDX-License-Identifier: GPL-2.0+ */ #include @@ -34,37 +18,66 @@ * are transmitted. The configurable test parameters are: * MIN_PACKET_LENGTH - minimum size of packet to transmit * MAX_PACKET_LENGTH - maximum size of packet to transmit - * TEST_NUM - number of tests + * CONFIG_SYS_POST_ETH_LOOPS - Number of test loops. Each loop + * is tested with a different frame length. Starting with + * MAX_PACKET_LENGTH and going down to MIN_PACKET_LENGTH. + * Defaults to 10 and can be overridden in the board config header. */ -#ifdef CONFIG_POST - #include -#if CONFIG_POST & CFG_POST_ETHER +#if CONFIG_POST & CONFIG_SYS_POST_ETHER #include #include #include -#include <405_mal.h> -#include +#include +#include #include DECLARE_GLOBAL_DATA_PTR; +/* + * Get count of EMAC devices (doesn't have to be the max. possible number + * supported by the cpu) + * + * CONFIG_BOARD_EMAC_COUNT added so now a "dynamic" way to configure the + * EMAC count is possible. As it is needed for the Kilauea/Haleakala + * 405EX/405EXr eval board, using the same binary. + */ +#if defined(CONFIG_BOARD_EMAC_COUNT) +#define LAST_EMAC_NUM board_emac_count() +#else /* CONFIG_BOARD_EMAC_COUNT */ +#if defined(CONFIG_HAS_ETH3) +#define LAST_EMAC_NUM 4 +#elif defined(CONFIG_HAS_ETH2) +#define LAST_EMAC_NUM 3 +#elif defined(CONFIG_HAS_ETH1) +#define LAST_EMAC_NUM 2 +#else +#define LAST_EMAC_NUM 1 +#endif +#endif /* CONFIG_BOARD_EMAC_COUNT */ + #if defined(CONFIG_440SPE) || defined(CONFIG_440EPX) || defined(CONFIG_440GRX) #define SDR0_MFR_ETH_CLK_SEL_V(n) ((0x01<<27) / (n+1)) #endif #define MIN_PACKET_LENGTH 64 -#define MAX_PACKET_LENGTH 256 -#define TEST_NUM 1 +#define MAX_PACKET_LENGTH 1514 +#ifndef CONFIG_SYS_POST_ETH_LOOPS +#define CONFIG_SYS_POST_ETH_LOOPS 10 +#endif +#define PACKET_INCR ((MAX_PACKET_LENGTH - MIN_PACKET_LENGTH) / \ + CONFIG_SYS_POST_ETH_LOOPS) static volatile mal_desc_t tx __cacheline_aligned; static volatile mal_desc_t rx __cacheline_aligned; static char *tx_buf; static char *rx_buf; +int board_emac_count(void); + static void ether_post_init (int devnum, int hw_addr) { int i; @@ -87,17 +100,17 @@ static void ether_post_init (int devnum, int hw_addr) #if defined(CONFIG_440SPE) || defined(CONFIG_440EPX) || defined(CONFIG_440GRX) /* provide clocks for EMAC internal loopback */ - mfsdr (sdr_mfr, mfr); + mfsdr (SDR0_MFR, mfr); mfr |= SDR0_MFR_ETH_CLK_SEL_V(devnum); - mtsdr (sdr_mfr, mfr); + mtsdr (SDR0_MFR, mfr); sync (); #endif /* reset emac */ - out32 (EMAC_M0 + hw_addr, EMAC_M0_SRST); + out_be32 ((void*)(EMAC0_MR0 + hw_addr), EMAC_MR0_SRST); sync (); for (i = 0;; i++) { - if (!(in32 (EMAC_M0 + hw_addr) & EMAC_M0_SRST)) + if (!(in_be32 ((void*)(EMAC0_MR0 + hw_addr)) & EMAC_MR0_SRST)) break; if (i >= 1000) { printf ("Timeout resetting EMAC\n"); @@ -112,15 +125,15 @@ static void ether_post_init (int devnum, int hw_addr) mode_reg = 0x0; if (sysinfo.freqOPB <= 50000000); else if (sysinfo.freqOPB <= 66666667) - mode_reg |= EMAC_M1_OBCI_66; + mode_reg |= EMAC_MR1_OBCI_66; else if (sysinfo.freqOPB <= 83333333) - mode_reg |= EMAC_M1_OBCI_83; + mode_reg |= EMAC_MR1_OBCI_83; else if (sysinfo.freqOPB <= 100000000) - mode_reg |= EMAC_M1_OBCI_100; + mode_reg |= EMAC_MR1_OBCI_100; else - mode_reg |= EMAC_M1_OBCI_GT100; + mode_reg |= EMAC_MR1_OBCI_GT100; - out32 (EMAC_M1 + hw_addr, mode_reg); + out_be32 ((void*)(EMAC0_MR1 + hw_addr), mode_reg); #endif /* defined(CONFIG_440GX) || defined(CONFIG_440SP) */ @@ -128,13 +141,13 @@ static void ether_post_init (int devnum, int hw_addr) #if defined(CONFIG_440GX) || \ defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ defined(CONFIG_440SP) || defined(CONFIG_440SPE) - mtdcr (malmcr, MAL_CR_PLBB | MAL_CR_OPBBL | MAL_CR_LEA | + mtdcr (MAL0_CFG, MAL_CR_PLBB | MAL_CR_OPBBL | MAL_CR_LEA | MAL_CR_PLBLT_DEFAULT | 0x00330000); #else - mtdcr (malmcr, MAL_CR_PLBB | MAL_CR_OPBBL | MAL_CR_LEA | MAL_CR_PLBLT_DEFAULT); + mtdcr (MAL0_CFG, MAL_CR_PLBB | MAL_CR_OPBBL | MAL_CR_LEA | MAL_CR_PLBLT_DEFAULT); /* Errata 1.12: MAL_1 -- Disable MAL bursting */ if (get_pvr() == PVR_440GP_RB) { - mtdcr (malmcr, mfdcr(malmcr) & ~MAL_CR_PLBB); + mtdcr (MAL0_CFG, mfdcr(MAL0_CFG) & ~MAL_CR_PLBB); } #endif /* setup buffer descriptors */ @@ -145,81 +158,83 @@ static void ether_post_init (int devnum, int hw_addr) rx.ctrl = MAL_TX_CTRL_WRAP | MAL_RX_CTRL_EMPTY; rx.data_len = 0; rx.data_ptr = (char*)L1_CACHE_ALIGN((u32)rx_buf); + flush_dcache_range((u32)&rx, (u32)&rx + sizeof(mal_desc_t)); + flush_dcache_range((u32)&tx, (u32)&tx + sizeof(mal_desc_t)); switch (devnum) { case 1: /* setup MAL tx & rx channel pointers */ #if defined (CONFIG_405EP) || defined (CONFIG_440EP) || defined (CONFIG_440GR) - mtdcr (maltxctp2r, &tx); + mtdcr (MAL0_TXCTP2R, &tx); #else - mtdcr (maltxctp1r, &tx); + mtdcr (MAL0_TXCTP1R, &tx); #endif #if defined(CONFIG_440) - mtdcr (maltxbattr, 0x0); - mtdcr (malrxbattr, 0x0); + mtdcr (MAL0_TXBADDR, 0x0); + mtdcr (MAL0_RXBADDR, 0x0); #endif - mtdcr (malrxctp1r, &rx); + mtdcr (MAL0_RXCTP1R, &rx); /* set RX buffer size */ - mtdcr (malrcbs1, PKTSIZE_ALIGN / 16); + mtdcr (MAL0_RCBS1, PKTSIZE_ALIGN / 16); break; case 0: default: /* setup MAL tx & rx channel pointers */ #if defined(CONFIG_440) - mtdcr (maltxbattr, 0x0); - mtdcr (malrxbattr, 0x0); + mtdcr (MAL0_TXBADDR, 0x0); + mtdcr (MAL0_RXBADDR, 0x0); #endif - mtdcr (maltxctp0r, &tx); - mtdcr (malrxctp0r, &rx); + mtdcr (MAL0_TXCTP0R, &tx); + mtdcr (MAL0_RXCTP0R, &rx); /* set RX buffer size */ - mtdcr (malrcbs0, PKTSIZE_ALIGN / 16); + mtdcr (MAL0_RCBS0, PKTSIZE_ALIGN / 16); break; } /* Enable MAL transmit and receive channels */ #if defined(CONFIG_405EP) || defined(CONFIG_440EP) || defined(CONFIG_440GR) - mtdcr (maltxcasr, (MAL_TXRX_CASR >> (devnum*2))); + mtdcr (MAL0_TXCASR, (MAL_TXRX_CASR >> (devnum*2))); #else - mtdcr (maltxcasr, (MAL_TXRX_CASR >> devnum)); + mtdcr (MAL0_TXCASR, (MAL_TXRX_CASR >> devnum)); #endif - mtdcr (malrxcasr, (MAL_TXRX_CASR >> devnum)); + mtdcr (MAL0_RXCASR, (MAL_TXRX_CASR >> devnum)); /* set internal loopback mode */ -#ifdef CFG_POST_ETHER_EXT_LOOPBACK - out32 (EMAC_M1 + hw_addr, EMAC_M1_FDE | 0 | - EMAC_M1_RFS_4K | EMAC_M1_TX_FIFO_2K | - EMAC_M1_MF_100MBPS | EMAC_M1_IST | - in32 (EMAC_M1)); +#ifdef CONFIG_SYS_POST_ETHER_EXT_LOOPBACK + out_be32 ((void*)(EMAC0_MR1 + hw_addr), EMAC_MR1_FDE | 0 | + EMAC_MR1_RFS_4K | EMAC_MR1_TX_FIFO_2K | + EMAC_MR1_MF_100MBPS | EMAC_MR1_IST | + in_be32 ((void*)(EMAC0_MR1 + hw_addr))); #else - out32 (EMAC_M1 + hw_addr, EMAC_M1_FDE | EMAC_M1_ILE | - EMAC_M1_RFS_4K | EMAC_M1_TX_FIFO_2K | - EMAC_M1_MF_100MBPS | EMAC_M1_IST | - in32 (EMAC_M1)); + out_be32 ((void*)(EMAC0_MR1 + hw_addr), EMAC_MR1_FDE | EMAC_MR1_ILE | + EMAC_MR1_RFS_4K | EMAC_MR1_TX_FIFO_2K | + EMAC_MR1_MF_100MBPS | EMAC_MR1_IST | + in_be32 ((void*)(EMAC0_MR1 + hw_addr))); #endif /* set transmit enable & receive enable */ - out32 (EMAC_M0 + hw_addr, EMAC_M0_TXE | EMAC_M0_RXE); + out_be32 ((void*)(EMAC0_MR0 + hw_addr), EMAC_MR0_TXE | EMAC_MR0_RXE); /* enable broadcast address */ - out32 (EMAC_RXM + hw_addr, EMAC_RMR_BAE); + out_be32 ((void*)(EMAC0_RXM + hw_addr), EMAC_RMR_BAE); /* set transmit request threshold register */ - out32 (EMAC_TRTR + hw_addr, 0x18000000); /* 256 byte threshold */ + out_be32 ((void*)(EMAC0_TRTR + hw_addr), 0x18000000); /* 256 byte threshold */ /* set receive low/high water mark register */ #if defined(CONFIG_440) /* 440s has a 64 byte burst length */ - out32 (EMAC_RX_HI_LO_WMARK + hw_addr, 0x80009000); + out_be32 ((void*)(EMAC0_RX_HI_LO_WMARK + hw_addr), 0x80009000); #else /* 405s have a 16 byte burst length */ - out32 (EMAC_RX_HI_LO_WMARK + hw_addr, 0x0f002000); + out_be32 ((void*)(EMAC0_RX_HI_LO_WMARK + hw_addr), 0x0f002000); #endif /* defined(CONFIG_440) */ - out32 (EMAC_TXM1 + hw_addr, 0xf8640000); + out_be32 ((void*)(EMAC0_TMR1 + hw_addr), 0xf8640000); /* Set fifo limit entry in tx mode 0 */ - out32 (EMAC_TXM0 + hw_addr, 0x00000003); + out_be32 ((void*)(EMAC0_TMR0 + hw_addr), 0x00000003); /* Frame gap set */ - out32 (EMAC_I_FRAME_GAP_REG + hw_addr, 0x00000008); + out_be32 ((void*)(EMAC0_I_FRAME_GAP_REG + hw_addr), 0x00000008); sync (); } @@ -233,26 +248,26 @@ static void ether_post_halt (int devnum, int hw_addr) /* 1st reset MAL channel */ /* Note: writing a 0 to a channel has no effect */ #if defined(CONFIG_405EP) || defined(CONFIG_440EP) || defined(CONFIG_440GR) - mtdcr (maltxcarr, MAL_TXRX_CASR >> (devnum * 2)); + mtdcr (MAL0_TXCARR, MAL_TXRX_CASR >> (devnum * 2)); #else - mtdcr (maltxcarr, MAL_TXRX_CASR >> devnum); + mtdcr (MAL0_TXCARR, MAL_TXRX_CASR >> devnum); #endif - mtdcr (malrxcarr, MAL_TXRX_CASR >> devnum); + mtdcr (MAL0_RXCARR, MAL_TXRX_CASR >> devnum); /* wait for reset */ - while (mfdcr (malrxcasr) & (MAL_TXRX_CASR >> devnum)) { + while (mfdcr (MAL0_RXCASR) & (MAL_TXRX_CASR >> devnum)) { if (i++ >= 1000) break; udelay (1000); } /* emac reset */ - out32 (EMAC_M0 + hw_addr, EMAC_M0_SRST); + out_be32 ((void*)(EMAC0_MR0 + hw_addr), EMAC_MR0_SRST); #if defined(CONFIG_440SPE) || defined(CONFIG_440EPX) || defined(CONFIG_440GRX) /* remove clocks for EMAC internal loopback */ - mfsdr (sdr_mfr, mfr); + mfsdr (SDR0_MFR, mfr); mfr &= ~SDR0_MFR_ETH_CLK_SEL_V(devnum); - mtsdr (sdr_mfr, mfr); + mtsdr (SDR0_MFR, mfr); #endif } @@ -266,14 +281,17 @@ static void ether_post_send (int devnum, int hw_addr, void *packet, int length) return; } udelay (1000); + invalidate_dcache_range((u32)&tx, (u32)&tx + sizeof(mal_desc_t)); } tx.ctrl = MAL_TX_CTRL_READY | MAL_TX_CTRL_WRAP | MAL_TX_CTRL_LAST | EMAC_TX_CTRL_GFCS | EMAC_TX_CTRL_GP; tx.data_len = length; memcpy (tx.data_ptr, packet, length); + flush_dcache_range((u32)&tx, (u32)&tx + sizeof(mal_desc_t)); + flush_dcache_range((u32)tx.data_ptr, (u32)tx.data_ptr + length); sync (); - out32 (EMAC_TXM0 + hw_addr, in32 (EMAC_TXM0 + hw_addr) | EMAC_TXM0_GNP0); + out_be32 ((void*)(EMAC0_TMR0 + hw_addr), in_be32 ((void*)(EMAC0_TMR0 + hw_addr)) | EMAC_TMR0_GNP0); sync (); } @@ -288,13 +306,17 @@ static int ether_post_recv (int devnum, int hw_addr, void *packet, int max_lengt return 0; } udelay (1000); + invalidate_dcache_range((u32)&rx, (u32)&rx + sizeof(mal_desc_t)); } length = rx.data_len - 4; - if (length <= max_length) + if (length <= max_length) { + invalidate_dcache_range((u32)rx.data_ptr, (u32)rx.data_ptr + length); memcpy(packet, rx.data_ptr, length); + } sync (); rx.ctrl |= MAL_RX_CTRL_EMPTY; + flush_dcache_range((u32)&rx, (u32)&rx + sizeof(mal_desc_t)); sync (); return length; @@ -330,29 +352,27 @@ static int packet_check (char *packet, int length) return 0; } + char packet_send[MAX_PACKET_LENGTH]; + char packet_recv[MAX_PACKET_LENGTH]; static int test_ctlr (int devnum, int hw_addr) { int res = -1; - char packet_send[MAX_PACKET_LENGTH]; - char packet_recv[MAX_PACKET_LENGTH]; int length; - int i; int l; ether_post_init (devnum, hw_addr); - for (i = 0; i < TEST_NUM; i++) { - for (l = MIN_PACKET_LENGTH; l <= MAX_PACKET_LENGTH; l++) { - packet_fill (packet_send, l); + for (l = MAX_PACKET_LENGTH; l >= MIN_PACKET_LENGTH; + l -= PACKET_INCR) { + packet_fill (packet_send, l); - ether_post_send (devnum, hw_addr, packet_send, l); + ether_post_send (devnum, hw_addr, packet_send, l); - length = ether_post_recv (devnum, hw_addr, packet_recv, - sizeof (packet_recv)); + length = ether_post_recv (devnum, hw_addr, packet_recv, + sizeof (packet_recv)); - if (length != l || packet_check (packet_recv, length) < 0) { - goto Done; - } + if (length != l || packet_check (packet_recv, length) < 0) { + goto Done; } } @@ -372,10 +392,11 @@ Done: int ether_post_test (int flags) { int res = 0; + int i; /* Allocate tx & rx packet buffers */ - tx_buf = malloc (PKTSIZE_ALIGN + CFG_CACHELINE_SIZE); - rx_buf = malloc (PKTSIZE_ALIGN + CFG_CACHELINE_SIZE); + tx_buf = malloc (PKTSIZE_ALIGN + CONFIG_SYS_CACHELINE_SIZE); + rx_buf = malloc (PKTSIZE_ALIGN + CONFIG_SYS_CACHELINE_SIZE); if (!tx_buf || !rx_buf) { printf ("Failed to allocate packet buffers\n"); @@ -383,13 +404,10 @@ int ether_post_test (int flags) goto out_free; } - /* EMAC0 */ - if (test_ctlr (0, 0)) - res = -1; - - /* EMAC1 */ - if (test_ctlr (1, 0x100)) - res = -1; + for (i = 0; i < LAST_EMAC_NUM; i++) { + if (test_ctlr (i, i*0x100)) + res = -1; + } out_free: free (tx_buf); @@ -398,5 +416,4 @@ out_free: return res; } -#endif /* CONFIG_POST & CFG_POST_ETHER */ -#endif /* CONFIG_POST */ +#endif /* CONFIG_POST & CONFIG_SYS_POST_ETHER */