X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=post%2Fboard%2Flwmon5%2Fdsp.c;h=2f55f01ceb37347ebfc3115ff513f1e7efede8e1;hb=1a4596601fd395f3afb8f82f3f840c5e00bdd57a;hp=0e6d9084a319b04d3f93b63d921ad6bbe9cde591;hpb=cb5473205206c7f14cbb1e747f28ec75b48826e2;p=platform%2Fkernel%2Fu-boot.git

diff --git a/post/board/lwmon5/dsp.c b/post/board/lwmon5/dsp.c
index 0e6d908..2f55f01 100644
--- a/post/board/lwmon5/dsp.c
+++ b/post/board/lwmon5/dsp.c
@@ -3,23 +3,7 @@
  *
  * Developed for DENX Software Engineering GmbH
  *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * SPDX-License-Identifier:	GPL-2.0+
  */
 
 #include <common.h>
@@ -33,20 +17,37 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-#define DSP_STATUS_REG 0xC4000008
+#define DSP_STATUS_REG		0xC4000008
+#define FPGA_STATUS_REG		0xC400000C
 
 int dsp_post_test(int flags)
 {
+	uint   old_value;
 	uint   read_value;
 	int    ret;
 
+	/* momorize fpga status */
+	old_value = in_be32((void *)FPGA_STATUS_REG);
+	/* enable outputs */
+	out_be32((void *)FPGA_STATUS_REG, 0x30);
+
+	/* generate sync signal */
+	out_be32((void *)DSP_STATUS_REG, 0x300);
+	udelay(5);
+	out_be32((void *)DSP_STATUS_REG, 0);
+	udelay(500);
+
+	/* read status */
 	ret = 0;
 	read_value = in_be32((void *)DSP_STATUS_REG) & 0x3;
-	if (read_value != 0x3) {
+	if (read_value != 0x03) {
 		post_log("\nDSP status read %08X\n", read_value);
 		ret = 1;
 	}
 
+	/* restore fpga status */
+	out_be32((void *)FPGA_STATUS_REG, old_value);
+
 	return ret;
 }