X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=opcodes%2Farm-dis.c;h=8f399fbfafe7d848abc2f83d928f04400ce17614;hb=6622a3046a1bc94add0dba0d18529babb9d30026;hp=ba1644307b5d260e9d4ed4249433b01e1e28709e;hpb=e3e535bc5863ec5a183bfaabcd5d1d36a129305a;p=platform%2Fupstream%2Fbinutils.git diff --git a/opcodes/arm-dis.c b/opcodes/arm-dis.c index ba16443..8f399fb 100644 --- a/opcodes/arm-dis.c +++ b/opcodes/arm-dis.c @@ -1,6 +1,5 @@ /* Instruction printing code for the ARM - Copyright 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, - 2004, 2005, 2006, 2007, 2008, 2009 Free Software Foundation, Inc. + Copyright (C) 1994-2014 Free Software Foundation, Inc. Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org) Modification by James G. Smith (jsmith@cygnus.co.uk) @@ -45,6 +44,31 @@ #define NUM_ELEM(a) (sizeof (a) / sizeof (a)[0]) #endif +/* Cached mapping symbol state. */ +enum map_type +{ + MAP_ARM, + MAP_THUMB, + MAP_DATA +}; + +struct arm_private_data +{ + /* The features to use when disassembling optional instructions. */ + arm_feature_set features; + + /* Whether any mapping symbols are present in the provided symbol + table. -1 if we do not know yet, otherwise 0 or 1. */ + int has_mapping_symbols; + + /* Track the last type (although this doesn't seem to be useful) */ + enum map_type last_type; + + /* Tracking symbol table information */ + int last_mapping_sym; + bfd_vma last_mapping_addr; +}; + struct opcode32 { unsigned long arch; /* Architecture defining this insn. */ @@ -66,7 +90,8 @@ struct opcode16 %c print condition code (always bits 28-31 in ARM mode) %q print shifter argument - %u print condition code (unconditional in ARM mode) + %u print condition code (unconditional in ARM mode, + UNPREDICTABLE if not AL in Thumb) %A print address for ldc/stc/ldf/stf instruction %B print vstm/vldm register list %I print cirrus signed shift immediate: bits 0..3|4..6 @@ -75,6 +100,7 @@ struct opcode16 %Q print floating point precision in ldf/stf insn %R print floating point rounding mode + %c print as a condition code (for vsel) %r print as an ARM register %R as %<>r but r15 is UNPREDICTABLE %ru as %<>r but each u register must be unique. @@ -291,6 +317,8 @@ static const struct opcode32 coprocessor_opcodes[] = {FPU_NEON_EXT_V1, 0x0e400b10, 0x0fd00f10, "vmov%c.8\t%16-19,7D[%5,6,21d], %12-15r"}, {FPU_NEON_EXT_V1, 0x0e500b10, 0x0f500f10, "vmov%c.%23?us8\t%12-15r, %16-19,7D[%5,6,21d]"}, /* Half-precision conversion instructions. */ + {FPU_VFP_EXT_ARMV8, 0x0eb20b40, 0x0fbf0f50, "vcvt%7?tb%c.f64.f16\t%z1, %y0"}, + {FPU_VFP_EXT_ARMV8, 0x0eb30b40, 0x0fbf0f50, "vcvt%7?tb%c.f16.f64\t%y1, %z0"}, {FPU_VFP_EXT_FP16, 0x0eb20a40, 0x0fbf0f50, "vcvt%7?tb%c.f32.f16\t%y1, %y0"}, {FPU_VFP_EXT_FP16, 0x0eb30a40, 0x0fbf0f50, "vcvt%7?tb%c.f16.f32\t%y1, %y0"}, @@ -459,11 +487,26 @@ static const struct opcode32 coprocessor_opcodes[] = {FPU_VFP_EXT_FMA, 0x0e900a00, 0x0fb00f50, "vfnms%c.f32\t%y1, %y2, %y0"}, {FPU_VFP_EXT_FMA, 0x0e900b00, 0x0fb00f50, "vfnms%c.f64\t%z1, %z2, %z0"}, + /* FP v5. */ + {FPU_VFP_EXT_ARMV8, 0xfe000a00, 0xff800f00, "vsel%20-21c%u.f32\t%y1, %y2, %y0"}, + {FPU_VFP_EXT_ARMV8, 0xfe000b00, 0xff800f00, "vsel%20-21c%u.f64\t%z1, %z2, %z0"}, + {FPU_VFP_EXT_ARMV8, 0xfe800a00, 0xffb00f40, "vmaxnm%u.f32\t%y1, %y2, %y0"}, + {FPU_VFP_EXT_ARMV8, 0xfe800b00, 0xffb00f40, "vmaxnm%u.f64\t%z1, %z2, %z0"}, + {FPU_VFP_EXT_ARMV8, 0xfe800a40, 0xffb00f40, "vminnm%u.f32\t%y1, %y2, %y0"}, + {FPU_VFP_EXT_ARMV8, 0xfe800b40, 0xffb00f40, "vminnm%u.f64\t%z1, %z2, %z0"}, + {FPU_VFP_EXT_ARMV8, 0xfebc0a40, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f32\t%y1, %y0"}, + {FPU_VFP_EXT_ARMV8, 0xfebc0b40, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f64\t%y1, %z0"}, + {FPU_VFP_EXT_ARMV8, 0x0eb60a40, 0x0fbe0f50, "vrint%7,16??xzr%c.f32\t%y1, %y0"}, + {FPU_VFP_EXT_ARMV8, 0x0eb60b40, 0x0fbe0f50, "vrint%7,16??xzr%c.f64\t%z1, %z0"}, + {FPU_VFP_EXT_ARMV8, 0xfeb80a40, 0xffbc0f50, "vrint%16-17?mpna%u.f32\t%y1, %y0"}, + {FPU_VFP_EXT_ARMV8, 0xfeb80b40, 0xffbc0f50, "vrint%16-17?mpna%u.f64\t%z1, %z0"}, + /* Generic coprocessor instructions. */ { 0, SENTINEL_GENERIC_START, 0, "" }, {ARM_EXT_V5E, 0x0c400000, 0x0ff00000, "mcrr%c\t%8-11d, %4-7d, %12-15R, %16-19r, cr%0-3d"}, {ARM_EXT_V5E, 0x0c500000, 0x0ff00000, "mrrc%c\t%8-11d, %4-7d, %12-15Ru, %16-19Ru, cr%0-3d"}, {ARM_EXT_V2, 0x0e000000, 0x0f000010, "cdp%c\t%8-11d, %20-23d, cr%12-15d, cr%16-19d, cr%0-3d, {%5-7d}"}, + {ARM_EXT_V2, 0x0e10f010, 0x0f10f010, "mrc%c\t%8-11d, %21-23d, APSR_nzcv, cr%16-19d, cr%0-3d, {%5-7d}"}, {ARM_EXT_V2, 0x0e100010, 0x0f100010, "mrc%c\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"}, {ARM_EXT_V2, 0x0e000010, 0x0f100010, "mcr%c\t%8-11d, %21-23d, %12-15R, cr%16-19d, cr%0-3d, {%5-7d}"}, {ARM_EXT_V2, 0x0c000000, 0x0e100000, "stc%22'l%c\t%8-11d, cr%12-15d, %A"}, @@ -492,6 +535,8 @@ static const struct opcode32 coprocessor_opcodes[] = %% % %c print condition code + %u print condition code (unconditional in ARM mode, + UNPREDICTABLE if not AL in Thumb) %A print v{st,ld}[1234] operands %B print v{st,ld}[1234] any one operands %C print v{st,ld}[1234] single->all operands @@ -537,6 +582,15 @@ static const struct opcode32 neon_opcodes[] = {FPU_NEON_EXT_FMA, 0xf2200c10, 0xffa00f10, "vfms%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"}, /* Two registers, miscellaneous. */ + {FPU_NEON_EXT_ARMV8, 0xf3ba0400, 0xffbf0c10, "vrint%7-9?p?m?zaxn%u.f32\t%12-15,22R, %0-3,5R"}, + {FPU_NEON_EXT_ARMV8, 0xf3bb0000, 0xffbf0c10, "vcvt%8-9?mpna%u.%7?us32.f32\t%12-15,22R, %0-3,5R"}, + {FPU_CRYPTO_EXT_ARMV8, 0xf3b00300, 0xffbf0fd0, "aese%u.8\t%12-15,22Q, %0-3,5Q"}, + {FPU_CRYPTO_EXT_ARMV8, 0xf3b00340, 0xffbf0fd0, "aesd%u.8\t%12-15,22Q, %0-3,5Q"}, + {FPU_CRYPTO_EXT_ARMV8, 0xf3b00380, 0xffbf0fd0, "aesmc%u.8\t%12-15,22Q, %0-3,5Q"}, + {FPU_CRYPTO_EXT_ARMV8, 0xf3b003c0, 0xffbf0fd0, "aesimc%u.8\t%12-15,22Q, %0-3,5Q"}, + {FPU_CRYPTO_EXT_ARMV8, 0xf3b902c0, 0xffbf0fd0, "sha1h%u.32\t%12-15,22Q, %0-3,5Q"}, + {FPU_CRYPTO_EXT_ARMV8, 0xf3ba0380, 0xffbf0fd0, "sha1su1%u.32\t%12-15,22Q, %0-3,5Q"}, + {FPU_CRYPTO_EXT_ARMV8, 0xf3ba03c0, 0xffbf0fd0, "sha256su0%u.32\t%12-15,22Q, %0-3,5Q"}, {FPU_NEON_EXT_V1, 0xf2880a10, 0xfebf0fd0, "vmovl%c.%24?us8\t%12-15,22Q, %0-3,5D"}, {FPU_NEON_EXT_V1, 0xf2900a10, 0xfebf0fd0, "vmovl%c.%24?us16\t%12-15,22Q, %0-3,5D"}, {FPU_NEON_EXT_V1, 0xf2a00a10, 0xfebf0fd0, "vmovl%c.%24?us32\t%12-15,22Q, %0-3,5D"}, @@ -572,6 +626,15 @@ static const struct opcode32 neon_opcodes[] = {FPU_NEON_EXT_V1, 0xf3b30600, 0xffb30e10, "vcvt%c.%7-8?usff%18-19Sa.%7-8?ffus%18-19Sa\t%12-15,22R, %0-3,5R"}, /* Three registers of the same length. */ + {FPU_CRYPTO_EXT_ARMV8, 0xf2000c40, 0xffb00f50, "sha1c%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"}, + {FPU_CRYPTO_EXT_ARMV8, 0xf2100c40, 0xffb00f50, "sha1p%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"}, + {FPU_CRYPTO_EXT_ARMV8, 0xf2200c40, 0xffb00f50, "sha1m%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"}, + {FPU_CRYPTO_EXT_ARMV8, 0xf2300c40, 0xffb00f50, "sha1su0%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"}, + {FPU_CRYPTO_EXT_ARMV8, 0xf3000c40, 0xffb00f50, "sha256h%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"}, + {FPU_CRYPTO_EXT_ARMV8, 0xf3100c40, 0xffb00f50, "sha256h2%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"}, + {FPU_CRYPTO_EXT_ARMV8, 0xf3200c40, 0xffb00f50, "sha256su1%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"}, + {FPU_NEON_EXT_ARMV8, 0xf3000f10, 0xffa00f10, "vmaxnm%u.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"}, + {FPU_NEON_EXT_ARMV8, 0xf3200f10, 0xffa00f10, "vminnm%u.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"}, {FPU_NEON_EXT_V1, 0xf2000110, 0xffb00f10, "vand%c\t%12-15,22R, %16-19,7R, %0-3,5R"}, {FPU_NEON_EXT_V1, 0xf2100110, 0xffb00f10, "vbic%c\t%12-15,22R, %16-19,7R, %0-3,5R"}, {FPU_NEON_EXT_V1, 0xf2200110, 0xffb00f10, "vorr%c\t%12-15,22R, %16-19,7R, %0-3,5R"}, @@ -648,7 +711,7 @@ static const struct opcode32 neon_opcodes[] = {FPU_NEON_EXT_V1, 0xf2880850, 0xfeb80fd0, "vqrshrun%c.s16\t%12-15,22D, %0-3,5Q, #%16-18e"}, {FPU_NEON_EXT_V1, 0xf2880910, 0xfeb80fd0, "vqshrn%c.%24?us16\t%12-15,22D, %0-3,5Q, #%16-18e"}, {FPU_NEON_EXT_V1, 0xf2880950, 0xfeb80fd0, "vqrshrn%c.%24?us16\t%12-15,22D, %0-3,5Q, #%16-18e"}, - {FPU_NEON_EXT_V1, 0xf2880a10, 0xfeb80fd0, "vshll%c.%24?us8\t%12-15,22D, %0-3,5Q, #%16-18d"}, + {FPU_NEON_EXT_V1, 0xf2880a10, 0xfeb80fd0, "vshll%c.%24?us8\t%12-15,22Q, %0-3,5D, #%16-18d"}, {FPU_NEON_EXT_V1, 0xf2900810, 0xffb00fd0, "vshrn%c.i32\t%12-15,22D, %0-3,5Q, #%16-19e"}, {FPU_NEON_EXT_V1, 0xf2900850, 0xffb00fd0, "vrshrn%c.i32\t%12-15,22D, %0-3,5Q, #%16-19e"}, {FPU_NEON_EXT_V1, 0xf2880510, 0xffb80f90, "vshl%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18d"}, @@ -659,7 +722,7 @@ static const struct opcode32 neon_opcodes[] = {FPU_NEON_EXT_V1, 0xf2900850, 0xfeb00fd0, "vqrshrun%c.s32\t%12-15,22D, %0-3,5Q, #%16-19e"}, {FPU_NEON_EXT_V1, 0xf2900910, 0xfeb00fd0, "vqshrn%c.%24?us32\t%12-15,22D, %0-3,5Q, #%16-19e"}, {FPU_NEON_EXT_V1, 0xf2900950, 0xfeb00fd0, "vqrshrn%c.%24?us32\t%12-15,22D, %0-3,5Q, #%16-19e"}, - {FPU_NEON_EXT_V1, 0xf2900a10, 0xfeb00fd0, "vshll%c.%24?us16\t%12-15,22D, %0-3,5Q, #%16-19d"}, + {FPU_NEON_EXT_V1, 0xf2900a10, 0xfeb00fd0, "vshll%c.%24?us16\t%12-15,22Q, %0-3,5D, #%16-19d"}, {FPU_NEON_EXT_V1, 0xf2880010, 0xfeb80f90, "vshr%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"}, {FPU_NEON_EXT_V1, 0xf2880110, 0xfeb80f90, "vsra%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"}, {FPU_NEON_EXT_V1, 0xf2880210, 0xfeb80f90, "vrshr%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"}, @@ -671,7 +734,7 @@ static const struct opcode32 neon_opcodes[] = {FPU_NEON_EXT_V1, 0xf3900410, 0xffb00f90, "vsri%c.16\t%12-15,22R, %0-3,5R, #%16-19e"}, {FPU_NEON_EXT_V1, 0xf3900510, 0xffb00f90, "vsli%c.16\t%12-15,22R, %0-3,5R, #%16-19d"}, {FPU_NEON_EXT_V1, 0xf3900610, 0xffb00f90, "vqshlu%c.s16\t%12-15,22R, %0-3,5R, #%16-19d"}, - {FPU_NEON_EXT_V1, 0xf2a00a10, 0xfea00fd0, "vshll%c.%24?us32\t%12-15,22D, %0-3,5Q, #%16-20d"}, + {FPU_NEON_EXT_V1, 0xf2a00a10, 0xfea00fd0, "vshll%c.%24?us32\t%12-15,22Q, %0-3,5D, #%16-20d"}, {FPU_NEON_EXT_V1, 0xf2900010, 0xfeb00f90, "vshr%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"}, {FPU_NEON_EXT_V1, 0xf2900110, 0xfeb00f90, "vsra%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"}, {FPU_NEON_EXT_V1, 0xf2900210, 0xfeb00f90, "vrshr%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"}, @@ -702,6 +765,7 @@ static const struct opcode32 neon_opcodes[] = {FPU_NEON_EXT_V1, 0xf2a00e10, 0xfea00e90, "vcvt%c.%24,8?usff32.%24,8?ffus32\t%12-15,22R, %0-3,5R, #%16-20e"}, /* Three registers of different lengths. */ + {FPU_CRYPTO_EXT_ARMV8, 0xf2a00e00, 0xfeb00f50, "vmull%c.p64\t%12-15,22Q, %16-19,7D, %0-3,5D"}, {FPU_NEON_EXT_V1, 0xf2800e00, 0xfea00f50, "vmull%c.p%20S0\t%12-15,22Q, %16-19,7D, %0-3,5D"}, {FPU_NEON_EXT_V1, 0xf2800400, 0xff800f50, "vaddhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"}, {FPU_NEON_EXT_V1, 0xf2800600, 0xff800f50, "vsubhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"}, @@ -791,6 +855,7 @@ static const struct opcode32 neon_opcodes[] = %P print address for pli instruction. %r print as an ARM register + %T print as an ARM register + 1 %R as %r but r15 is UNPREDICTABLE %{r|R}u as %{r|R} but if matches the other %u field then is UNPREDICTABLE %{r|R}U as %{r|R} but if matches the other %U field then is UNPREDICTABLE @@ -805,12 +870,15 @@ static const struct opcode32 neon_opcodes[] = %e print arm SMI operand (bits 0..7,8..19). %E print the LSB and WIDTH fields of a BFI or BFC instruction. - %V print the 16-bit immediate field of a MOVT or MOVW instruction. */ + %V print the 16-bit immediate field of a MOVT or MOVW instruction. + %R print the SPSR/CPSR or banked register of an MRS. */ static const struct opcode32 arm_opcodes[] = { /* ARM instructions. */ {ARM_EXT_V1, 0xe1a00000, 0xffffffff, "nop\t\t\t; (mov r0, r0)"}, + {ARM_EXT_V1, 0xe7f000f0, 0xfff000f0, "udf\t#%e"}, + {ARM_EXT_V4T | ARM_EXT_V5, 0x012FFF10, 0x0ffffff0, "bx%c\t%0-3r"}, {ARM_EXT_V2, 0x00000090, 0x0fe000f0, "mul%20's%c\t%16-19R, %0-3R, %8-11R"}, {ARM_EXT_V2, 0x00200090, 0x0fe000f0, "mla%20's%c\t%16-19R, %0-3R, %8-11R, %12-15R"}, @@ -818,9 +886,47 @@ static const struct opcode32 arm_opcodes[] = {ARM_EXT_V3M, 0x00800090, 0x0fa000f0, "%22?sumull%20's%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"}, {ARM_EXT_V3M, 0x00a00090, 0x0fa000f0, "%22?sumlal%20's%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"}, + /* V8 instructions. */ + {ARM_EXT_V8, 0x0320f005, 0x0fffffff, "sevl"}, + {ARM_EXT_V8, 0xe1000070, 0xfff000f0, "hlt\t0x%16-19X%12-15X%8-11X%0-3X"}, + {ARM_EXT_V8, 0x01800e90, 0x0ff00ff0, "stlex%c\t%12-15r, %0-3r, [%16-19R]"}, + {ARM_EXT_V8, 0x01900e9f, 0x0ff00fff, "ldaex%c\t%12-15r, [%16-19R]"}, + {ARM_EXT_V8, 0x01a00e90, 0x0ff00ff0, "stlexd%c\t%12-15r, %0-3r, %0-3T, [%16-19R]"}, + {ARM_EXT_V8, 0x01b00e9f, 0x0ff00fff, "ldaexd%c\t%12-15r, %12-15T, [%16-19R]"}, + {ARM_EXT_V8, 0x01c00e90, 0x0ff00ff0, "stlexb%c\t%12-15r, %0-3r, [%16-19R]"}, + {ARM_EXT_V8, 0x01d00e9f, 0x0ff00fff, "ldaexb%c\t%12-15r, [%16-19R]"}, + {ARM_EXT_V8, 0x01e00e90, 0x0ff00ff0, "stlexh%c\t%12-15r, %0-3r, [%16-19R]"}, + {ARM_EXT_V8, 0x01f00e9f, 0x0ff00fff, "ldaexh%c\t%12-15r, [%16-19R]"}, + {ARM_EXT_V8, 0x0180fc90, 0x0ff0fff0, "stl%c\t%0-3r, [%16-19R]"}, + {ARM_EXT_V8, 0x01900c9f, 0x0ff00fff, "lda%c\t%12-15r, [%16-19R]"}, + {ARM_EXT_V8, 0x01c0fc90, 0x0ff0fff0, "stlb%c\t%0-3r, [%16-19R]"}, + {ARM_EXT_V8, 0x01d00c9f, 0x0ff00fff, "ldab%c\t%12-15r, [%16-19R]"}, + {ARM_EXT_V8, 0x01e0fc90, 0x0ff0fff0, "stlh%c\t%0-3r, [%16-19R]"}, + {ARM_EXT_V8, 0x01f00c9f, 0x0ff00fff, "ldaexh%c\t%12-15r, [%16-19R]"}, + /* CRC32 instructions. */ + {CRC_EXT_ARMV8, 0xe1000040, 0xfff00ff0, "crc32b\t%12-15R, %16-19R, %0-3R"}, + {CRC_EXT_ARMV8, 0xe1200040, 0xfff00ff0, "crc32h\t%12-15R, %16-19R, %0-3R"}, + {CRC_EXT_ARMV8, 0xe1400040, 0xfff00ff0, "crc32w\t%12-15R, %16-19R, %0-3R"}, + {CRC_EXT_ARMV8, 0xe1000240, 0xfff00ff0, "crc32cb\t%12-15R, %16-19R, %0-3R"}, + {CRC_EXT_ARMV8, 0xe1200240, 0xfff00ff0, "crc32ch\t%12-15R, %16-19R, %0-3R"}, + {CRC_EXT_ARMV8, 0xe1400240, 0xfff00ff0, "crc32cw\t%12-15R, %16-19R, %0-3R"}, + + /* Virtualization Extension instructions. */ + {ARM_EXT_VIRT, 0x0160006e, 0x0fffffff, "eret%c"}, + {ARM_EXT_VIRT, 0x01400070, 0x0ff000f0, "hvc%c\t%e"}, + + /* Integer Divide Extension instructions. */ + {ARM_EXT_ADIV, 0x0710f010, 0x0ff0f0f0, "sdiv%c\t%16-19r, %0-3r, %8-11r"}, + {ARM_EXT_ADIV, 0x0730f010, 0x0ff0f0f0, "udiv%c\t%16-19r, %0-3r, %8-11r"}, + + /* MP Extension instructions. */ + {ARM_EXT_MP, 0xf410f000, 0xfc70f000, "pldw\t%a"}, + /* V7 instructions. */ {ARM_EXT_V7, 0xf450f000, 0xfd70f000, "pli\t%P"}, {ARM_EXT_V7, 0x0320f0f0, 0x0ffffff0, "dbg%c\t#%0-3d"}, + {ARM_EXT_V8, 0xf57ff051, 0xfffffff3, "dmb\t%U"}, + {ARM_EXT_V8, 0xf57ff041, 0xfffffff3, "dsb\t%U"}, {ARM_EXT_V7, 0xf57ff050, 0xfffffff0, "dmb\t%U"}, {ARM_EXT_V7, 0xf57ff040, 0xfffffff0, "dsb\t%U"}, {ARM_EXT_V7, 0xf57ff060, 0xfffffff0, "isb\t%U"}, @@ -829,8 +935,8 @@ static const struct opcode32 arm_opcodes[] = {ARM_EXT_V6T2, 0x07c0001f, 0x0fe0007f, "bfc%c\t%12-15R, %E"}, {ARM_EXT_V6T2, 0x07c00010, 0x0fe00070, "bfi%c\t%12-15R, %0-3r, %E"}, {ARM_EXT_V6T2, 0x00600090, 0x0ff000f0, "mls%c\t%16-19R, %0-3R, %8-11R, %12-15R"}, - {ARM_EXT_V6T2, 0x006000b0, 0x0f7000f0, "strht%c\t%12-15R, %S"}, - + {ARM_EXT_V6T2, 0x002000b0, 0x0f3000f0, "strht%c\t%12-15R, %S"}, + {ARM_EXT_V6T2, 0x00300090, 0x0f3000f0, UNDEFINED_INSTRUCTION }, {ARM_EXT_V6T2, 0x00300090, 0x0f300090, "ldr%6's%5?hbt%c\t%12-15R, %S"}, @@ -839,8 +945,8 @@ static const struct opcode32 arm_opcodes[] = {ARM_EXT_V6T2, 0x06ff0f30, 0x0fff0ff0, "rbit%c\t%12-15R, %0-3R"}, {ARM_EXT_V6T2, 0x07a00050, 0x0fa00070, "%22?usbfx%c\t%12-15r, %0-3r, #%7-11d, #%16-20W"}, - /* ARM V6Z instructions. */ - {ARM_EXT_V6Z, 0x01600070, 0x0ff000f0, "smc%c\t%e"}, + /* ARM Security extension instructions. */ + {ARM_EXT_SEC, 0x01600070, 0x0ff000f0, "smc%c\t%e"}, /* ARM V6K instructions. */ {ARM_EXT_V6K, 0xf57ff01f, 0xffffffff, "clrex"}, @@ -871,40 +977,40 @@ static const struct opcode32 arm_opcodes[] = {ARM_EXT_V6, 0x01900f9f, 0x0ff00fff, "ldrex%c\tr%12-15d, [%16-19R]"}, {ARM_EXT_V6, 0x06200f10, 0x0ff00ff0, "qadd16%c\t%12-15R, %16-19R, %0-3R"}, {ARM_EXT_V6, 0x06200f90, 0x0ff00ff0, "qadd8%c\t%12-15R, %16-19R, %0-3R"}, - {ARM_EXT_V6, 0x06200f30, 0x0ff00ff0, "qaddsubx%c\t%12-15R, %16-19R, %0-3R"}, + {ARM_EXT_V6, 0x06200f30, 0x0ff00ff0, "qasx%c\t%12-15R, %16-19R, %0-3R"}, {ARM_EXT_V6, 0x06200f70, 0x0ff00ff0, "qsub16%c\t%12-15R, %16-19R, %0-3R"}, {ARM_EXT_V6, 0x06200ff0, 0x0ff00ff0, "qsub8%c\t%12-15R, %16-19R, %0-3R"}, - {ARM_EXT_V6, 0x06200f50, 0x0ff00ff0, "qsubaddx%c\t%12-15R, %16-19R, %0-3R"}, + {ARM_EXT_V6, 0x06200f50, 0x0ff00ff0, "qsax%c\t%12-15R, %16-19R, %0-3R"}, {ARM_EXT_V6, 0x06100f10, 0x0ff00ff0, "sadd16%c\t%12-15R, %16-19R, %0-3R"}, {ARM_EXT_V6, 0x06100f90, 0x0ff00ff0, "sadd8%c\t%12-15R, %16-19R, %0-3R"}, - {ARM_EXT_V6, 0x06100f30, 0x0ff00ff0, "saddaddx%c\t%12-15R, %16-19R, %0-3R"}, + {ARM_EXT_V6, 0x06100f30, 0x0ff00ff0, "sasx%c\t%12-15R, %16-19R, %0-3R"}, {ARM_EXT_V6, 0x06300f10, 0x0ff00ff0, "shadd16%c\t%12-15R, %16-19R, %0-3R"}, {ARM_EXT_V6, 0x06300f90, 0x0ff00ff0, "shadd8%c\t%12-15R, %16-19R, %0-3R"}, - {ARM_EXT_V6, 0x06300f30, 0x0ff00ff0, "shaddsubx%c\t%12-15R, %16-19R, %0-3R"}, + {ARM_EXT_V6, 0x06300f30, 0x0ff00ff0, "shasx%c\t%12-15R, %16-19R, %0-3R"}, {ARM_EXT_V6, 0x06300f70, 0x0ff00ff0, "shsub16%c\t%12-15R, %16-19R, %0-3R"}, {ARM_EXT_V6, 0x06300ff0, 0x0ff00ff0, "shsub8%c\t%12-15R, %16-19R, %0-3R"}, - {ARM_EXT_V6, 0x06300f50, 0x0ff00ff0, "shsubaddx%c\t%12-15R, %16-19R, %0-3R"}, + {ARM_EXT_V6, 0x06300f50, 0x0ff00ff0, "shsax%c\t%12-15R, %16-19R, %0-3R"}, {ARM_EXT_V6, 0x06100f70, 0x0ff00ff0, "ssub16%c\t%12-15R, %16-19R, %0-3R"}, {ARM_EXT_V6, 0x06100ff0, 0x0ff00ff0, "ssub8%c\t%12-15R, %16-19R, %0-3R"}, - {ARM_EXT_V6, 0x06100f50, 0x0ff00ff0, "ssubaddx%c\t%12-15R, %16-19R, %0-3R"}, + {ARM_EXT_V6, 0x06100f50, 0x0ff00ff0, "ssax%c\t%12-15R, %16-19R, %0-3R"}, {ARM_EXT_V6, 0x06500f10, 0x0ff00ff0, "uadd16%c\t%12-15R, %16-19R, %0-3R"}, {ARM_EXT_V6, 0x06500f90, 0x0ff00ff0, "uadd8%c\t%12-15R, %16-19R, %0-3R"}, - {ARM_EXT_V6, 0x06500f30, 0x0ff00ff0, "uaddsubx%c\t%12-15R, %16-19R, %0-3R"}, + {ARM_EXT_V6, 0x06500f30, 0x0ff00ff0, "uasx%c\t%12-15R, %16-19R, %0-3R"}, {ARM_EXT_V6, 0x06700f10, 0x0ff00ff0, "uhadd16%c\t%12-15R, %16-19R, %0-3R"}, {ARM_EXT_V6, 0x06700f90, 0x0ff00ff0, "uhadd8%c\t%12-15R, %16-19R, %0-3R"}, - {ARM_EXT_V6, 0x06700f30, 0x0ff00ff0, "uhaddsubx%c\t%12-15R, %16-19R, %0-3R"}, + {ARM_EXT_V6, 0x06700f30, 0x0ff00ff0, "uhasx%c\t%12-15R, %16-19R, %0-3R"}, {ARM_EXT_V6, 0x06700f70, 0x0ff00ff0, "uhsub16%c\t%12-15R, %16-19R, %0-3R"}, {ARM_EXT_V6, 0x06700ff0, 0x0ff00ff0, "uhsub8%c\t%12-15R, %16-19R, %0-3R"}, - {ARM_EXT_V6, 0x06700f50, 0x0ff00ff0, "uhsubaddx%c\t%12-15R, %16-19R, %0-3R"}, + {ARM_EXT_V6, 0x06700f50, 0x0ff00ff0, "uhsax%c\t%12-15R, %16-19R, %0-3R"}, {ARM_EXT_V6, 0x06600f10, 0x0ff00ff0, "uqadd16%c\t%12-15R, %16-19R, %0-3R"}, {ARM_EXT_V6, 0x06600f90, 0x0ff00ff0, "uqadd8%c\t%12-15R, %16-19R, %0-3R"}, - {ARM_EXT_V6, 0x06600f30, 0x0ff00ff0, "uqaddsubx%c\t%12-15R, %16-19R, %0-3R"}, + {ARM_EXT_V6, 0x06600f30, 0x0ff00ff0, "uqasx%c\t%12-15R, %16-19R, %0-3R"}, {ARM_EXT_V6, 0x06600f70, 0x0ff00ff0, "uqsub16%c\t%12-15R, %16-19R, %0-3R"}, {ARM_EXT_V6, 0x06600ff0, 0x0ff00ff0, "uqsub8%c\t%12-15R, %16-19R, %0-3R"}, - {ARM_EXT_V6, 0x06600f50, 0x0ff00ff0, "uqsubaddx%c\t%12-15R, %16-19R, %0-3R"}, + {ARM_EXT_V6, 0x06600f50, 0x0ff00ff0, "uqsax%c\t%12-15R, %16-19R, %0-3R"}, {ARM_EXT_V6, 0x06500f70, 0x0ff00ff0, "usub16%c\t%12-15R, %16-19R, %0-3R"}, {ARM_EXT_V6, 0x06500ff0, 0x0ff00ff0, "usub8%c\t%12-15R, %16-19R, %0-3R"}, - {ARM_EXT_V6, 0x06500f50, 0x0ff00ff0, "usubaddx%c\t%12-15R, %16-19R, %0-3R"}, + {ARM_EXT_V6, 0x06500f50, 0x0ff00ff0, "usax%c\t%12-15R, %16-19R, %0-3R"}, {ARM_EXT_V6, 0x06bf0f30, 0x0fff0ff0, "rev%c\t%12-15R, %0-3R"}, {ARM_EXT_V6, 0x06bf0fb0, 0x0fff0ff0, "rev16%c\t%12-15R, %0-3R"}, {ARM_EXT_V6, 0x06ff0fb0, 0x0fff0ff0, "revsh%c\t%12-15R, %0-3R"}, @@ -1073,8 +1179,9 @@ static const struct opcode32 arm_opcodes[] = {ARM_EXT_V1, 0x00e00000, 0x0fe00010, "rsc%20's%c\t%12-15r, %16-19r, %o"}, {ARM_EXT_V1, 0x00e00010, 0x0fe00090, "rsc%20's%c\t%12-15R, %16-19R, %o"}, - {ARM_EXT_V3, 0x0120f000, 0x0db0f000, "msr%c\t%22?SCPSR%C, %o"}, - {ARM_EXT_V3, 0x010f0000, 0x0fbf0fff, "mrs%c\t%12-15R, %22?SCPSR"}, + {ARM_EXT_VIRT, 0x0120f200, 0x0fb0f200, "msr%c\t%C, %0-3r"}, + {ARM_EXT_V3, 0x0120f000, 0x0db0f000, "msr%c\t%C, %o"}, + {ARM_EXT_V3, 0x01000000, 0x0fb00cff, "mrs%c\t%12-15R, %R"}, {ARM_EXT_V1, 0x03000000, 0x0fe00000, "tst%p%c\t%16-19r, %o"}, {ARM_EXT_V1, 0x01000000, 0x0fe00010, "tst%p%c\t%16-19r, %o"}, @@ -1085,7 +1192,6 @@ static const struct opcode32 arm_opcodes[] = {ARM_EXT_V1, 0x01200010, 0x0fe00090, "teq%p%c\t%16-19R, %o"}, {ARM_EXT_V1, 0x03400000, 0x0fe00000, "cmp%p%c\t%16-19r, %o"}, - {ARM_EXT_V3, 0x01400000, 0x0ff00010, "mrs%c\t%12-15R, %22?SCPSR"}, {ARM_EXT_V1, 0x01400000, 0x0fe00010, "cmp%p%c\t%16-19r, %o"}, {ARM_EXT_V1, 0x01400010, 0x0fe00090, "cmp%p%c\t%16-19R, %o"}, @@ -1121,12 +1227,46 @@ static const struct opcode32 arm_opcodes[] = {ARM_EXT_V1, 0x04300000, 0x0d700000, "ldrt%c\t%12-15R, %a"}, {ARM_EXT_V1, 0x04100000, 0x0c500000, "ldr%c\t%12-15r, %a"}, + {ARM_EXT_V1, 0x092d0001, 0x0fffffff, "stmfd%c\t%16-19R!, %m"}, + {ARM_EXT_V1, 0x092d0002, 0x0fffffff, "stmfd%c\t%16-19R!, %m"}, + {ARM_EXT_V1, 0x092d0004, 0x0fffffff, "stmfd%c\t%16-19R!, %m"}, + {ARM_EXT_V1, 0x092d0008, 0x0fffffff, "stmfd%c\t%16-19R!, %m"}, + {ARM_EXT_V1, 0x092d0010, 0x0fffffff, "stmfd%c\t%16-19R!, %m"}, + {ARM_EXT_V1, 0x092d0020, 0x0fffffff, "stmfd%c\t%16-19R!, %m"}, + {ARM_EXT_V1, 0x092d0040, 0x0fffffff, "stmfd%c\t%16-19R!, %m"}, + {ARM_EXT_V1, 0x092d0080, 0x0fffffff, "stmfd%c\t%16-19R!, %m"}, + {ARM_EXT_V1, 0x092d0100, 0x0fffffff, "stmfd%c\t%16-19R!, %m"}, + {ARM_EXT_V1, 0x092d0200, 0x0fffffff, "stmfd%c\t%16-19R!, %m"}, + {ARM_EXT_V1, 0x092d0400, 0x0fffffff, "stmfd%c\t%16-19R!, %m"}, + {ARM_EXT_V1, 0x092d0800, 0x0fffffff, "stmfd%c\t%16-19R!, %m"}, + {ARM_EXT_V1, 0x092d1000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"}, + {ARM_EXT_V1, 0x092d2000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"}, + {ARM_EXT_V1, 0x092d4000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"}, + {ARM_EXT_V1, 0x092d8000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"}, {ARM_EXT_V1, 0x092d0000, 0x0fff0000, "push%c\t%m"}, {ARM_EXT_V1, 0x08800000, 0x0ff00000, "stm%c\t%16-19R%21'!, %m%22'^"}, {ARM_EXT_V1, 0x08000000, 0x0e100000, "stm%23?id%24?ba%c\t%16-19R%21'!, %m%22'^"}, + + {ARM_EXT_V1, 0x08bd0001, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"}, + {ARM_EXT_V1, 0x08bd0002, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"}, + {ARM_EXT_V1, 0x08bd0004, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"}, + {ARM_EXT_V1, 0x08bd0008, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"}, + {ARM_EXT_V1, 0x08bd0010, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"}, + {ARM_EXT_V1, 0x08bd0020, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"}, + {ARM_EXT_V1, 0x08bd0040, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"}, + {ARM_EXT_V1, 0x08bd0080, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"}, + {ARM_EXT_V1, 0x08bd0100, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"}, + {ARM_EXT_V1, 0x08bd0200, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"}, + {ARM_EXT_V1, 0x08bd0400, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"}, + {ARM_EXT_V1, 0x08bd0800, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"}, + {ARM_EXT_V1, 0x08bd1000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"}, + {ARM_EXT_V1, 0x08bd2000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"}, + {ARM_EXT_V1, 0x08bd4000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"}, + {ARM_EXT_V1, 0x08bd8000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"}, {ARM_EXT_V1, 0x08bd0000, 0x0fff0000, "pop%c\t%m"}, {ARM_EXT_V1, 0x08900000, 0x0f900000, "ldm%c\t%16-19R%21'!, %m%22'^"}, {ARM_EXT_V1, 0x08100000, 0x0e100000, "ldm%23?id%24?ba%c\t%16-19R%21'!, %m%22'^"}, + {ARM_EXT_V1, 0x0a000000, 0x0e000000, "b%24'l%c\t%b"}, {ARM_EXT_V1, 0x0f000000, 0x0f000000, "svc%c\t%0-23x"}, @@ -1151,6 +1291,7 @@ static const struct opcode32 arm_opcodes[] = %x print warning if conditional an not at end of IT block" %X print "\t; unpredictable " if conditional %I print IT instruction suffix and operands + %W print Thumb Writeback indicator for LDMIA %r print bitfield as an ARM register %d print bitfield as a decimal %H print (bitfield * 2) as a decimal @@ -1165,6 +1306,10 @@ static const struct opcode16 thumb_opcodes[] = { /* Thumb instructions. */ + /* ARM V8 instructions. */ + {ARM_EXT_V8, 0xbf50, 0xffff, "sevl%c"}, + {ARM_EXT_V8, 0xba80, 0xffc0, "hlt\t%0-5x"}, + /* ARM V6K no-argument instructions. */ {ARM_EXT_V6K, 0xbf00, 0xffff, "nop%c"}, {ARM_EXT_V6K, 0xbf10, 0xffff, "yield%c"}, @@ -1238,6 +1383,7 @@ static const struct opcode16 thumb_opcodes[] = {ARM_EXT_V4T, 0x5000, 0xFA00, "str%10'b%c\t%0-2r, [%3-5r, %6-8r]"}, {ARM_EXT_V4T, 0x5800, 0xFA00, "ldr%10'b%c\t%0-2r, [%3-5r, %6-8r]"}, /* format 1 */ + {ARM_EXT_V4T, 0x0000, 0xFFC0, "mov%C\t%0-2r, %3-5r"}, {ARM_EXT_V4T, 0x0000, 0xF800, "lsl%C\t%0-2r, %3-5r, #%6-10d"}, {ARM_EXT_V4T, 0x0800, 0xF800, "lsr%C\t%0-2r, %3-5r, %s"}, {ARM_EXT_V4T, 0x1000, 0xF800, "asr%C\t%0-2r, %3-5r, %s"}, @@ -1264,10 +1410,11 @@ static const struct opcode16 thumb_opcodes[] = {ARM_EXT_V4T, 0xA800, 0xF800, "add%c\t%8-10r, sp, #%0-7W"}, /* format 15 */ {ARM_EXT_V4T, 0xC000, 0xF800, "stmia%c\t%8-10r!, %M"}, - {ARM_EXT_V4T, 0xC800, 0xF800, "ldmia%c\t%8-10r!, %M"}, + {ARM_EXT_V4T, 0xC800, 0xF800, "ldmia%c\t%8-10r%W, %M"}, /* format 17 */ {ARM_EXT_V4T, 0xDF00, 0xFF00, "svc%c\t%0-7d"}, /* format 16 */ + {ARM_EXT_V4T, 0xDE00, 0xFF00, "udf%c\t#%0-7d"}, {ARM_EXT_V4T, 0xDE00, 0xFE00, UNDEFINED_INSTRUCTION}, {ARM_EXT_V4T, 0xD000, 0xF000, "b%8-11c.n\t%0-7B%X"}, /* format 18 */ @@ -1293,8 +1440,10 @@ static const struct opcode16 thumb_opcodes[] = %M print a modified 12-bit immediate (same location) %J print a 16-bit immediate from hw1[3:0,10],hw2[14:12,7:0] %K print a 16-bit immediate from hw2[3:0],hw1[3:0],hw2[11:4] + %H print a 16-bit immediate from hw2[3:0],hw1[11:0] %S print a possibly-shifted Rm + %L print address for a ldrd/strd instruction %a print the address of a plain load/store %w print the width and signedness of a core load/store %m print register mask for ldm/stm @@ -1314,7 +1463,8 @@ static const struct opcode16 thumb_opcodes[] = %d print bitfield in decimal %W print bitfield*4 in decimal %r print bitfield as an ARM register - %R as %<>r bit r15 is UNPREDICTABLE + %R as %<>r but r15 is UNPREDICTABLE + %S as %<>R but r13 is UNPREDICTABLE %c print bitfield as a condition code %'c print specified char iff bitfield is all ones @@ -1331,15 +1481,53 @@ static const struct opcode16 thumb_opcodes[] = makes heavy use of special-case bit patterns. */ static const struct opcode32 thumb32_opcodes[] = { + /* V8 instructions. */ + {ARM_EXT_V8, 0xf3af8005, 0xffffffff, "sevl%c.w"}, + {ARM_EXT_V8, 0xf78f8000, 0xfffffffc, "dcps%0-1d"}, + {ARM_EXT_V8, 0xe8c00f8f, 0xfff00fff, "stlb%c\t%12-15r, [%16-19R]"}, + {ARM_EXT_V8, 0xe8c00f9f, 0xfff00fff, "stlh%c\t%12-15r, [%16-19R]"}, + {ARM_EXT_V8, 0xe8c00faf, 0xfff00fff, "stl%c\t%12-15r, [%16-19R]"}, + {ARM_EXT_V8, 0xe8c00fc0, 0xfff00ff0, "stlexb%c\t%0-3r, %12-15r, [%16-19R]"}, + {ARM_EXT_V8, 0xe8c00fd0, 0xfff00ff0, "stlexh%c\t%0-3r, %12-15r, [%16-19R]"}, + {ARM_EXT_V8, 0xe8c00fe0, 0xfff00ff0, "stlex%c\t%0-3r, %12-15r, [%16-19R]"}, + {ARM_EXT_V8, 0xe8c000f0, 0xfff000f0, "stlexd%c\t%0-3r, %12-15r, %8-11r, [%16-19R]"}, + {ARM_EXT_V8, 0xe8d00f8f, 0xfff00fff, "ldab%c\t%12-15r, [%16-19R]"}, + {ARM_EXT_V8, 0xe8d00f9f, 0xfff00fff, "ldah%c\t%12-15r, [%16-19R]"}, + {ARM_EXT_V8, 0xe8d00faf, 0xfff00fff, "lda%c\t%12-15r, [%16-19R]"}, + {ARM_EXT_V8, 0xe8d00fcf, 0xfff00fff, "ldaexb%c\t%12-15r, [%16-19R]"}, + {ARM_EXT_V8, 0xe8d00fdf, 0xfff00fff, "ldaexh%c\t%12-15r, [%16-19R]"}, + {ARM_EXT_V8, 0xe8d00fef, 0xfff00fff, "ldaex%c\t%12-15r, [%16-19R]"}, + {ARM_EXT_V8, 0xe8d000ff, 0xfff000ff, "ldaexd%c\t%12-15r, %8-11r, [%16-19R]"}, + + /* CRC32 instructions. */ + {CRC_EXT_ARMV8, 0xfac0f080, 0xfff0f0f0, "crc32b\t%8-11S, %16-19S, %0-3S"}, + {CRC_EXT_ARMV8, 0xfac0f090, 0xfff0f0f0, "crc32h\t%9-11S, %16-19S, %0-3S"}, + {CRC_EXT_ARMV8, 0xfac0f0a0, 0xfff0f0f0, "crc32w\t%8-11S, %16-19S, %0-3S"}, + {CRC_EXT_ARMV8, 0xfad0f080, 0xfff0f0f0, "crc32cb\t%8-11S, %16-19S, %0-3S"}, + {CRC_EXT_ARMV8, 0xfad0f090, 0xfff0f0f0, "crc32ch\t%8-11S, %16-19S, %0-3S"}, + {CRC_EXT_ARMV8, 0xfad0f0a0, 0xfff0f0f0, "crc32cw\t%8-11S, %16-19S, %0-3S"}, + /* V7 instructions. */ {ARM_EXT_V7, 0xf910f000, 0xff70f000, "pli%c\t%a"}, {ARM_EXT_V7, 0xf3af80f0, 0xfffffff0, "dbg%c\t#%0-3d"}, + {ARM_EXT_V8, 0xf3bf8f51, 0xfffffff3, "dmb%c\t%U"}, + {ARM_EXT_V8, 0xf3bf8f41, 0xfffffff3, "dsb%c\t%U"}, {ARM_EXT_V7, 0xf3bf8f50, 0xfffffff0, "dmb%c\t%U"}, {ARM_EXT_V7, 0xf3bf8f40, 0xfffffff0, "dsb%c\t%U"}, {ARM_EXT_V7, 0xf3bf8f60, 0xfffffff0, "isb%c\t%U"}, {ARM_EXT_DIV, 0xfb90f0f0, 0xfff0f0f0, "sdiv%c\t%8-11r, %16-19r, %0-3r"}, {ARM_EXT_DIV, 0xfbb0f0f0, 0xfff0f0f0, "udiv%c\t%8-11r, %16-19r, %0-3r"}, + /* Virtualization Extension instructions. */ + {ARM_EXT_VIRT, 0xf7e08000, 0xfff0f000, "hvc%c\t%V"}, + /* We skip ERET as that is SUBS pc, lr, #0. */ + + /* MP Extension instructions. */ + {ARM_EXT_MP, 0xf830f000, 0xff70f000, "pldw%c\t%a"}, + + /* Security extension instructions. */ + {ARM_EXT_SEC, 0xf7f08000, 0xfff0f000, "smc%c\t%K"}, + /* Instructions defined in the basic V6T2 set. */ {ARM_EXT_V6T2, 0xf3af8000, 0xffffffff, "nop%c.w"}, {ARM_EXT_V6T2, 0xf3af8001, 0xffffffff, "yield%c.w"}, @@ -1347,6 +1535,7 @@ static const struct opcode32 thumb32_opcodes[] = {ARM_EXT_V6T2, 0xf3af8003, 0xffffffff, "wfi%c.w"}, {ARM_EXT_V6T2, 0xf3af8004, 0xffffffff, "sev%c.w"}, {ARM_EXT_V6T2, 0xf3af8000, 0xffffff00, "nop%c.w\t{%0-7d}"}, + {ARM_EXT_V6T2, 0xf7f0a000, 0xfff0f000, "udf%c.w\t%H"}, {ARM_EXT_V6T2, 0xf3bf8f2f, 0xffffffff, "clrex%c"}, {ARM_EXT_V6T2, 0xf3af8400, 0xffffff1f, "cpsie.w\t%7'a%6'i%5'f%X"}, @@ -1354,7 +1543,7 @@ static const struct opcode32 thumb32_opcodes[] = {ARM_EXT_V6T2, 0xf3c08f00, 0xfff0ffff, "bxj%c\t%16-19r%x"}, {ARM_EXT_V6T2, 0xe810c000, 0xffd0ffff, "rfedb%c\t%16-19r%21'!"}, {ARM_EXT_V6T2, 0xe990c000, 0xffd0ffff, "rfeia%c\t%16-19r%21'!"}, - {ARM_EXT_V6T2, 0xf3ef8000, 0xffeff000, "mrs%c\t%8-11r, %D"}, + {ARM_EXT_V6T2, 0xf3e08000, 0xffe0f000, "mrs%c\t%8-11r, %D"}, {ARM_EXT_V6T2, 0xf3af8100, 0xffffffe0, "cps\t#%0-4d%X"}, {ARM_EXT_V6T2, 0xe8d0f000, 0xfff0fff0, "tbb%c\t[%16-19r, %0-3r]%x"}, {ARM_EXT_V6T2, 0xe8d0f010, 0xfff0fff0, "tbh%c\t[%16-19r, %0-3r, lsl #1]%x"}, @@ -1394,12 +1583,12 @@ static const struct opcode32 thumb32_opcodes[] = {ARM_EXT_V6T2, 0xfa90f090, 0xfff0f0f0, "rev16%c.w\t%8-11r, %16-19r"}, {ARM_EXT_V6T2, 0xfa90f0a0, 0xfff0f0f0, "rbit%c\t%8-11r, %16-19r"}, {ARM_EXT_V6T2, 0xfa90f0b0, 0xfff0f0f0, "revsh%c.w\t%8-11r, %16-19r"}, - {ARM_EXT_V6T2, 0xfaa0f000, 0xfff0f0f0, "saddsubx%c\t%8-11r, %16-19r, %0-3r"}, - {ARM_EXT_V6T2, 0xfaa0f010, 0xfff0f0f0, "qaddsubx%c\t%8-11r, %16-19r, %0-3r"}, - {ARM_EXT_V6T2, 0xfaa0f020, 0xfff0f0f0, "shaddsubx%c\t%8-11r, %16-19r, %0-3r"}, - {ARM_EXT_V6T2, 0xfaa0f040, 0xfff0f0f0, "uaddsubx%c\t%8-11r, %16-19r, %0-3r"}, - {ARM_EXT_V6T2, 0xfaa0f050, 0xfff0f0f0, "uqaddsubx%c\t%8-11r, %16-19r, %0-3r"}, - {ARM_EXT_V6T2, 0xfaa0f060, 0xfff0f0f0, "uhaddsubx%c\t%8-11r, %16-19r, %0-3r"}, + {ARM_EXT_V6T2, 0xfaa0f000, 0xfff0f0f0, "sasx%c\t%8-11r, %16-19r, %0-3r"}, + {ARM_EXT_V6T2, 0xfaa0f010, 0xfff0f0f0, "qasx%c\t%8-11r, %16-19r, %0-3r"}, + {ARM_EXT_V6T2, 0xfaa0f020, 0xfff0f0f0, "shasx%c\t%8-11r, %16-19r, %0-3r"}, + {ARM_EXT_V6T2, 0xfaa0f040, 0xfff0f0f0, "uasx%c\t%8-11r, %16-19r, %0-3r"}, + {ARM_EXT_V6T2, 0xfaa0f050, 0xfff0f0f0, "uqasx%c\t%8-11r, %16-19r, %0-3r"}, + {ARM_EXT_V6T2, 0xfaa0f060, 0xfff0f0f0, "uhasx%c\t%8-11r, %16-19r, %0-3r"}, {ARM_EXT_V6T2, 0xfaa0f080, 0xfff0f0f0, "sel%c\t%8-11r, %16-19r, %0-3r"}, {ARM_EXT_V6T2, 0xfab0f080, 0xfff0f0f0, "clz%c\t%8-11r, %16-19r"}, {ARM_EXT_V6T2, 0xfac0f000, 0xfff0f0f0, "ssub8%c\t%8-11r, %16-19r, %0-3r"}, @@ -1414,12 +1603,12 @@ static const struct opcode32 thumb32_opcodes[] = {ARM_EXT_V6T2, 0xfad0f040, 0xfff0f0f0, "usub16%c\t%8-11r, %16-19r, %0-3r"}, {ARM_EXT_V6T2, 0xfad0f050, 0xfff0f0f0, "uqsub16%c\t%8-11r, %16-19r, %0-3r"}, {ARM_EXT_V6T2, 0xfad0f060, 0xfff0f0f0, "uhsub16%c\t%8-11r, %16-19r, %0-3r"}, - {ARM_EXT_V6T2, 0xfae0f000, 0xfff0f0f0, "ssubaddx%c\t%8-11r, %16-19r, %0-3r"}, - {ARM_EXT_V6T2, 0xfae0f010, 0xfff0f0f0, "qsubaddx%c\t%8-11r, %16-19r, %0-3r"}, - {ARM_EXT_V6T2, 0xfae0f020, 0xfff0f0f0, "shsubaddx%c\t%8-11r, %16-19r, %0-3r"}, - {ARM_EXT_V6T2, 0xfae0f040, 0xfff0f0f0, "usubaddx%c\t%8-11r, %16-19r, %0-3r"}, - {ARM_EXT_V6T2, 0xfae0f050, 0xfff0f0f0, "uqsubaddx%c\t%8-11r, %16-19r, %0-3r"}, - {ARM_EXT_V6T2, 0xfae0f060, 0xfff0f0f0, "uhsubaddx%c\t%8-11r, %16-19r, %0-3r"}, + {ARM_EXT_V6T2, 0xfae0f000, 0xfff0f0f0, "ssax%c\t%8-11r, %16-19r, %0-3r"}, + {ARM_EXT_V6T2, 0xfae0f010, 0xfff0f0f0, "qsax%c\t%8-11r, %16-19r, %0-3r"}, + {ARM_EXT_V6T2, 0xfae0f020, 0xfff0f0f0, "shsax%c\t%8-11r, %16-19r, %0-3r"}, + {ARM_EXT_V6T2, 0xfae0f040, 0xfff0f0f0, "usax%c\t%8-11r, %16-19r, %0-3r"}, + {ARM_EXT_V6T2, 0xfae0f050, 0xfff0f0f0, "uqsax%c\t%8-11r, %16-19r, %0-3r"}, + {ARM_EXT_V6T2, 0xfae0f060, 0xfff0f0f0, "uhsax%c\t%8-11r, %16-19r, %0-3r"}, {ARM_EXT_V6T2, 0xfb00f000, 0xfff0f0f0, "mul%c.w\t%8-11r, %16-19r, %0-3r"}, {ARM_EXT_V6T2, 0xfb70f000, 0xfff0f0f0, "usad8%c\t%8-11r, %16-19r, %0-3r"}, {ARM_EXT_V6T2, 0xfa00f000, 0xffe0f0f0, "lsl%20's%c.w\t%8-11R, %16-19R, %0-3R"}, @@ -1461,7 +1650,6 @@ static const struct opcode32 thumb32_opcodes[] = {ARM_EXT_V6T2, 0xfbe00000, 0xfff000f0, "umlal%c\t%12-15R, %8-11R, %16-19R, %0-3R"}, {ARM_EXT_V6T2, 0xfbe00060, 0xfff000f0, "umaal%c\t%12-15R, %8-11R, %16-19R, %0-3R"}, {ARM_EXT_V6T2, 0xe8500f00, 0xfff00f00, "ldrex%c\t%12-15r, [%16-19r, #%0-7W]"}, - {ARM_EXT_V6T2, 0xf7f08000, 0xfff0f000, "smc%c\t%K"}, {ARM_EXT_V6T2, 0xf04f0000, 0xfbef8000, "mov%20's%c.w\t%8-11r, %M"}, {ARM_EXT_V6T2, 0xf06f0000, 0xfbef8000, "mvn%20's%c.w\t%8-11r, %M"}, {ARM_EXT_V6T2, 0xf810f000, 0xff70f000, "pld%c\t%a"}, @@ -1514,10 +1702,10 @@ static const struct opcode32 thumb32_opcodes[] = {ARM_EXT_V6T2, 0xe9100000, 0xffd00000, "ldmdb%c\t%16-19r%21'!, %m"}, {ARM_EXT_V6T2, 0xe9c00000, 0xffd000ff, "strd%c\t%12-15r, %8-11r, [%16-19r]"}, {ARM_EXT_V6T2, 0xe9d00000, 0xffd000ff, "ldrd%c\t%12-15r, %8-11r, [%16-19r]"}, - {ARM_EXT_V6T2, 0xe9400000, 0xff500000, "strd%c\t%12-15r, %8-11r, [%16-19r, #%23`-%0-7W]%21'!"}, - {ARM_EXT_V6T2, 0xe9500000, 0xff500000, "ldrd%c\t%12-15r, %8-11r, [%16-19r, #%23`-%0-7W]%21'!"}, - {ARM_EXT_V6T2, 0xe8600000, 0xff700000, "strd%c\t%12-15r, %8-11r, [%16-19r], #%23`-%0-7W"}, - {ARM_EXT_V6T2, 0xe8700000, 0xff700000, "ldrd%c\t%12-15r, %8-11r, [%16-19r], #%23`-%0-7W"}, + {ARM_EXT_V6T2, 0xe9400000, 0xff500000, "strd%c\t%12-15r, %8-11r, [%16-19r, #%23`-%0-7W]%21'!%L"}, + {ARM_EXT_V6T2, 0xe9500000, 0xff500000, "ldrd%c\t%12-15r, %8-11r, [%16-19r, #%23`-%0-7W]%21'!%L"}, + {ARM_EXT_V6T2, 0xe8600000, 0xff700000, "strd%c\t%12-15r, %8-11r, [%16-19r], #%23`-%0-7W%L"}, + {ARM_EXT_V6T2, 0xe8700000, 0xff700000, "ldrd%c\t%12-15r, %8-11r, [%16-19r], #%23`-%0-7W%L"}, {ARM_EXT_V6T2, 0xf8000000, 0xff100000, "str%w%c.w\t%12-15r, %a"}, {ARM_EXT_V6T2, 0xf8100000, 0xfe100000, "ldr%w%c.w\t%12-15r, %a"}, @@ -1528,7 +1716,7 @@ static const struct opcode32 thumb32_opcodes[] = {ARM_EXT_V6T2, 0xf0009000, 0xf800d000, "b%c.w\t%B%x"}, /* These have been 32-bit since the invention of Thumb. */ - {ARM_EXT_V4T, 0xf000c000, 0xf800d000, "blx%c\t%B%x"}, + {ARM_EXT_V4T, 0xf000c000, 0xf800d001, "blx%c\t%B%x"}, {ARM_EXT_V4T, 0xf000d000, 0xf800d000, "bl%c\t%B%x"}, /* Fallback. */ @@ -1606,18 +1794,9 @@ static unsigned int ifthen_next_state; /* The address of the insn for which the IT state is valid. */ static bfd_vma ifthen_address; #define IFTHEN_COND ((ifthen_state >> 4) & 0xf) - -/* Cached mapping symbol state. */ -enum map_type -{ - MAP_ARM, - MAP_THUMB, - MAP_DATA -}; - -enum map_type last_type; -int last_mapping_sym = -1; -bfd_vma last_mapping_addr = 0; +/* Indicates that the current Conditional state is unconditional or outside + an IT block. */ +#define COND_UNCOND 16 /* Functions. */ @@ -1750,7 +1929,8 @@ print_insn_coprocessor (bfd_vma pc, fprintf_ftype func = info->fprintf_func; unsigned long mask; unsigned long value = 0; - unsigned long allowed_arches = ((arm_feature_set *) info->private_data)->coproc; + struct arm_private_data *private_data = info->private_data; + unsigned long allowed_arches = private_data->features.coproc; int cond; for (insn = coprocessor_opcodes; insn->assembler; insn++) @@ -1776,7 +1956,7 @@ print_insn_coprocessor (bfd_vma pc, continue; case SENTINEL_GENERIC_START: - allowed_arches = ((arm_feature_set *) info->private_data)->core; + allowed_arches = private_data->features.core; continue; default: @@ -1795,7 +1975,7 @@ print_insn_coprocessor (bfd_vma pc, if (ifthen_state) cond = IFTHEN_COND; else - cond = 16; + cond = COND_UNCOND; } else { @@ -1804,13 +1984,13 @@ print_insn_coprocessor (bfd_vma pc, if ((given & 0xf0000000) == 0xf0000000) { mask |= 0xf0000000; - cond = 16; + cond = COND_UNCOND; } else { cond = (given >> 28) & 0xf; if (cond == 0xe) - cond = 16; + cond = COND_UNCOND; } } @@ -1833,7 +2013,7 @@ print_insn_coprocessor (bfd_vma pc, case 'A': { int rn = (given >> 16) & 0xf; - int offset = given & 0xff; + bfd_vma offset = given & 0xff; func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]); @@ -1851,8 +2031,10 @@ print_insn_coprocessor (bfd_vma pc, { if (offset) func (stream, ", #%d]%s", - offset, + (int) offset, WRITEBACK_BIT_SET ? "!" : ""); + else if (NEGATIVE_BIT_SET) + func (stream, ", #-0]"); else func (stream, "]"); } @@ -1863,19 +2045,27 @@ print_insn_coprocessor (bfd_vma pc, if (WRITEBACK_BIT_SET) { if (offset) - func (stream, ", #%d", offset); + func (stream, ", #%d", (int) offset); + else if (NEGATIVE_BIT_SET) + func (stream, ", #-0"); } else { - func (stream, ", {%d}", offset); + func (stream, ", {%s%d}", + (NEGATIVE_BIT_SET && !offset) ? "-" : "", + (int) offset); value_in_comment = offset; } } if (rn == 15 && (PRE_BIT_SET || WRITEBACK_BIT_SET)) { func (stream, "\t; "); - info->print_address_func (offset + pc - + info->bytes_per_chunk * 2, info); + /* For unaligned PCs, apply off-by-alignment + correction. */ + info->print_address_func (offset + pc + + info->bytes_per_chunk * 2 + - (pc & 3), + info); } } break; @@ -1894,6 +2084,11 @@ print_insn_coprocessor (bfd_vma pc, } break; + case 'u': + if (cond != COND_UNCOND) + is_unpredictable = TRUE; + + /* Fall through. */ case 'c': func (stream, "%s", arm_conditional[cond]); break; @@ -2057,6 +2252,31 @@ print_insn_coprocessor (bfd_vma pc, func (stream, "0x%lx", (value & 0xffffffffUL)); break; + case 'c': + switch (value) + { + case 0: + func (stream, "eq"); + break; + + case 1: + func (stream, "vs"); + break; + + case 2: + func (stream, "ge"); + break; + + case 3: + func (stream, "gt"); + break; + + default: + func (stream, "??"); + break; + } + break; + case '`': c++; if (value == 0) @@ -2174,7 +2394,7 @@ print_insn_coprocessor (bfd_vma pc, { /* given (20, 23) | given (0, 3) */ value = ((given >> 16) & 0xf0) | (given & 0xf); - func (stream, "%d", value); + func (stream, "%d", (int) value); } break; @@ -2285,7 +2505,7 @@ print_arm_address (bfd_vma pc, struct disassemble_info *info, long given) { void *stream = info->stream; fprintf_ftype func = info->fprintf_func; - int offset = 0; + bfd_vma offset = 0; if (((given & 0x000f0000) == 0x000f0000) && ((given & 0x02000000) == 0)) @@ -2296,11 +2516,13 @@ print_arm_address (bfd_vma pc, struct disassemble_info *info, long given) if (PRE_BIT_SET) { - if (NEGATIVE_BIT_SET) - offset = - offset; + /* Pre-indexed. Elide offset of positive zero when + non-writeback. */ + if (WRITEBACK_BIT_SET || NEGATIVE_BIT_SET || offset) + func (stream, ", #%s%d", NEGATIVE_BIT_SET ? "-" : "", (int) offset); - /* Pre-indexed. */ - func (stream, ", #%d]", offset); + if (NEGATIVE_BIT_SET) + offset = -offset; offset += pc + 8; @@ -2308,12 +2530,11 @@ print_arm_address (bfd_vma pc, struct disassemble_info *info, long given) being used. Probably a very dangerous thing for the programmer to do, but who are we to argue ? */ - if (WRITEBACK_BIT_SET) - func (stream, "!"); + func (stream, "]%s", WRITEBACK_BIT_SET ? "!" : ""); } else /* Post indexed. */ { - func (stream, "], #%d", offset); + func (stream, "], #%s%d", NEGATIVE_BIT_SET ? "-" : "", (int) offset); /* Ie ignore the offset. */ offset = pc + 8; @@ -2332,15 +2553,14 @@ print_arm_address (bfd_vma pc, struct disassemble_info *info, long given) { if ((given & 0x02000000) == 0) { + /* Elide offset of positive zero when non-writeback. */ offset = given & 0xfff; - if (offset) - func (stream, ", #%s%d", - NEGATIVE_BIT_SET ? "-" : "", offset); + if (WRITEBACK_BIT_SET || NEGATIVE_BIT_SET || offset) + func (stream, ", #%s%d", NEGATIVE_BIT_SET ? "-" : "", (int) offset); } else { - func (stream, ", %s", - NEGATIVE_BIT_SET ? "-" : ""); + func (stream, ", %s", NEGATIVE_BIT_SET ? "-" : ""); arm_decode_shift (given, func, stream, TRUE); } @@ -2351,12 +2571,10 @@ print_arm_address (bfd_vma pc, struct disassemble_info *info, long given) { if ((given & 0x02000000) == 0) { + /* Always show offset. */ offset = given & 0xfff; - if (offset) - func (stream, "], #%s%d", - NEGATIVE_BIT_SET ? "-" : "", offset); - else - func (stream, "]"); + func (stream, "], #%s%d", + NEGATIVE_BIT_SET ? "-" : "", (int) offset); } else { @@ -2365,6 +2583,8 @@ print_arm_address (bfd_vma pc, struct disassemble_info *info, long given) arm_decode_shift (given, func, stream, TRUE); } } + if (NEGATIVE_BIT_SET) + offset = -offset; } return (signed long) offset; @@ -2405,6 +2625,7 @@ print_insn_neon (struct disassemble_info *info, long given, bfd_boolean thumb) if ((given & insn->mask) == insn->value) { signed long value_in_comment = 0; + bfd_boolean is_unpredictable = FALSE; const char *c; for (c = insn->assembler; *c; c++) @@ -2417,6 +2638,11 @@ print_insn_neon (struct disassemble_info *info, long given, bfd_boolean thumb) func (stream, "%%"); break; + case 'u': + if (thumb && ifthen_state) + is_unpredictable = TRUE; + + /* Fall through. */ case 'c': if (thumb && ifthen_state) func (stream, "%s", arm_conditional[IFTHEN_COND]); @@ -2457,7 +2683,7 @@ print_insn_neon (struct disassemble_info *info, long given, bfd_boolean thumb) func (stream, "d%d-d%d", rd, rd + n - 1); func (stream, "}, [%s", arm_regnames[rn]); if (align) - func (stream, ", :%d", 32 << align); + func (stream, " :%d", 32 << align); func (stream, "]"); if (rm == 0xd) func (stream, "!"); @@ -2532,7 +2758,7 @@ print_insn_neon (struct disassemble_info *info, long given, bfd_boolean thumb) rd + i * stride, idx); func (stream, "}, [%s", arm_regnames[rn]); if (align) - func (stream, ", :%d", align); + func (stream, " :%d", align); func (stream, "]"); if (rm == 0xd) func (stream, "!"); @@ -2573,9 +2799,9 @@ print_insn_neon (struct disassemble_info *info, long given, bfd_boolean thumb) if (type == 3) align = (size > 1) ? align >> 1 : align; if (type == 2 || (type == 0 && !size)) - func (stream, ", :", align); + func (stream, " :", align); else - func (stream, ", :%d", align); + func (stream, " :%d", align); } func (stream, "]"); if (rm == 0xd) @@ -2708,7 +2934,8 @@ print_insn_neon (struct disassemble_info *info, long given, bfd_boolean thumb) } else func (stream, "#%ld\t; 0x%.8lx", - (long) (NEGATIVE_BIT_SET ? value | ~0xffffffffL : value), + (long) (((value & 0x80000000L) != 0) + ? value | ~0xffffffffL : value), value); break; @@ -2735,7 +2962,7 @@ print_insn_neon (struct disassemble_info *info, long given, bfd_boolean thumb) func (stream, "{d%d-d%d}", regno, regno + num); } break; - + case '0': case '1': case '2': case '3': case '4': case '5': case '6': case '7': case '8': case '9': @@ -2829,12 +3056,83 @@ print_insn_neon (struct disassemble_info *info, long given, bfd_boolean thumb) if (value_in_comment > 32 || value_in_comment < -16) func (stream, "\t; 0x%lx", value_in_comment); + if (is_unpredictable) + func (stream, UNPREDICTABLE_INSTRUCTION); + return TRUE; } } return FALSE; } +/* Return the name of a v7A special register. */ + +static const char * +banked_regname (unsigned reg) +{ + switch (reg) + { + case 15: return "CPSR"; + case 32: return "R8_usr"; + case 33: return "R9_usr"; + case 34: return "R10_usr"; + case 35: return "R11_usr"; + case 36: return "R12_usr"; + case 37: return "SP_usr"; + case 38: return "LR_usr"; + case 40: return "R8_fiq"; + case 41: return "R9_fiq"; + case 42: return "R10_fiq"; + case 43: return "R11_fiq"; + case 44: return "R12_fiq"; + case 45: return "SP_fiq"; + case 46: return "LR_fiq"; + case 48: return "LR_irq"; + case 49: return "SP_irq"; + case 50: return "LR_svc"; + case 51: return "SP_svc"; + case 52: return "LR_abt"; + case 53: return "SP_abt"; + case 54: return "LR_und"; + case 55: return "SP_und"; + case 60: return "LR_mon"; + case 61: return "SP_mon"; + case 62: return "ELR_hyp"; + case 63: return "SP_hyp"; + case 79: return "SPSR"; + case 110: return "SPSR_fiq"; + case 112: return "SPSR_irq"; + case 114: return "SPSR_svc"; + case 116: return "SPSR_abt"; + case 118: return "SPSR_und"; + case 124: return "SPSR_mon"; + case 126: return "SPSR_hyp"; + default: return NULL; + } +} + +/* Return the name of the DMB/DSB option. */ +static const char * +data_barrier_option (unsigned option) +{ + switch (option & 0xf) + { + case 0xf: return "sy"; + case 0xe: return "st"; + case 0xd: return "ld"; + case 0xb: return "ish"; + case 0xa: return "ishst"; + case 0x9: return "ishld"; + case 0x7: return "un"; + case 0x6: return "unst"; + case 0x5: return "nshld"; + case 0x3: return "osh"; + case 0x2: return "oshst"; + case 0x1: return "oshld"; + default: return NULL; + } +} + /* Print one ARM instruction from PC on INFO->STREAM. */ static void @@ -2843,6 +3141,7 @@ print_insn_arm (bfd_vma pc, struct disassemble_info *info, long given) const struct opcode32 *insn; void *stream = info->stream; fprintf_ftype func = info->fprintf_func; + struct arm_private_data *private_data = info->private_data; if (print_insn_coprocessor (pc, info, given, FALSE)) return; @@ -2855,7 +3154,7 @@ print_insn_arm (bfd_vma pc, struct disassemble_info *info, long given) if ((given & insn->mask) != insn->value) continue; - if ((insn->arch & ((arm_feature_set *) info->private_data)->core) == 0) + if ((insn->arch & private_data->features.core) == 0) continue; /* Special case: an instruction with all bits set in the condition field @@ -2899,22 +3198,25 @@ print_insn_arm (bfd_vma pc, struct disassemble_info *info, long given) if ((given & 0x004f0000) == 0x004f0000) { /* PC relative with immediate offset. */ - int offset = ((given & 0xf00) >> 4) | (given & 0xf); - - if (NEGATIVE_BIT_SET) - offset = - offset; + bfd_vma offset = ((given & 0xf00) >> 4) | (given & 0xf); if (PRE_BIT_SET) { - if (offset) - func (stream, "[pc, #%d]\t; ", offset); + /* Elide positive zero offset. */ + if (offset || NEGATIVE_BIT_SET) + func (stream, "[pc, #%s%d]\t; ", + NEGATIVE_BIT_SET ? "-" : "", (int) offset); else - func (stream, "[pc]\t; "); + func (stream, "[pc]\t; "); + if (NEGATIVE_BIT_SET) + offset = -offset; info->print_address_func (offset + pc + 8, info); } else { - func (stream, "[pc], #%d", offset); + /* Always show the offset. */ + func (stream, "[pc], #%s%d", + NEGATIVE_BIT_SET ? "-" : "", (int) offset); if (! allow_unpredictable) is_unpredictable = TRUE; } @@ -2923,9 +3225,6 @@ print_insn_arm (bfd_vma pc, struct disassemble_info *info, long given) { int offset = ((given & 0xf00) >> 4) | (given & 0xf); - if (NEGATIVE_BIT_SET) - offset = - offset; - func (stream, "[%s", arm_regnames[(given >> 16) & 0xf]); @@ -2933,13 +3232,15 @@ print_insn_arm (bfd_vma pc, struct disassemble_info *info, long given) { if (IMMEDIATE_BIT_SET) { - if (WRITEBACK_BIT_SET) - /* Immediate Pre-indexed. */ - /* PR 10924: Offset must be printed, even if it is zero. */ - func (stream, ", #%d", offset); - else if (offset) - /* Immediate Offset: printing zero offset is optional. */ - func (stream, ", #%d", offset); + /* Elide offset for non-writeback + positive zero. */ + if (WRITEBACK_BIT_SET || NEGATIVE_BIT_SET + || offset) + func (stream, ", #%s%d", + NEGATIVE_BIT_SET ? "-" : "", offset); + + if (NEGATIVE_BIT_SET) + offset = -offset; value_in_comment = offset; } @@ -2967,7 +3268,10 @@ print_insn_arm (bfd_vma pc, struct disassemble_info *info, long given) { /* Immediate Post-indexed. */ /* PR 10924: Offset must be printed, even if it is zero. */ - func (stream, "], #%d", offset); + func (stream, "], #%s%d", + NEGATIVE_BIT_SET ? "-" : "", offset); + if (NEGATIVE_BIT_SET) + offset = -offset; value_in_comment = offset; } else @@ -3001,7 +3305,7 @@ print_insn_arm (bfd_vma pc, struct disassemble_info *info, long given) case 'b': { - int disp = (((given & 0xffffff) ^ 0x800000) - 0x800000); + bfd_vma disp = (((given & 0xffffff) ^ 0x800000) - 0x800000); info->print_address_func (disp * 4 + pc + 8, info); } break; @@ -3039,13 +3343,23 @@ print_insn_arm (bfd_vma pc, struct disassemble_info *info, long given) case 'o': if ((given & 0x02000000) != 0) { - int rotate = (given & 0xf00) >> 7; - int immed = (given & 0xff); - - immed = (((immed << (32 - rotate)) - | (immed >> rotate)) & 0xffffffff); - func (stream, "#%d", immed); - value_in_comment = immed; + unsigned int rotate = (given & 0xf00) >> 7; + unsigned int immed = (given & 0xff); + unsigned int a, i; + + a = (((immed << (32 - rotate)) + | (immed >> rotate)) & 0xffffffff); + /* If there is another encoding with smaller rotate, + the rotate should be specified directly. */ + for (i = 0; i < 32; i += 2) + if ((a << i | a >> (32 - i)) <= 0xff) + break; + + if (i != rotate) + func (stream, "#%d, %d", immed, rotate); + else + func (stream, "#%d", a); + value_in_comment = a; } else arm_decode_shift (given, func, stream, TRUE); @@ -3057,7 +3371,7 @@ print_insn_arm (bfd_vma pc, struct disassemble_info *info, long given) /* The p-variants of tst/cmp/cmn/teq are the pre-V6 mechanism for setting PSR flag bits. They are obsolete in V6 onwards. */ - if (((((arm_feature_set *) info->private_data)->core) & ARM_EXT_V6) == 0) + if ((private_data->features.core & ARM_EXT_V6) == 0) func (stream, "p"); } break; @@ -3081,7 +3395,7 @@ print_insn_arm (bfd_vma pc, struct disassemble_info *info, long given) { if (offset) func (stream, ", #%d]%s", - value_in_comment, + (int) value_in_comment, WRITEBACK_BIT_SET ? "!" : ""); else func (stream, "]"); @@ -3093,11 +3407,11 @@ print_insn_arm (bfd_vma pc, struct disassemble_info *info, long given) if (WRITEBACK_BIT_SET) { if (offset) - func (stream, ", #%d", value_in_comment); + func (stream, ", #%d", (int) value_in_comment); } else { - func (stream, ", {%d}", offset); + func (stream, ", {%d}", (int) offset); value_in_comment = offset; } } @@ -3128,27 +3442,52 @@ print_insn_arm (bfd_vma pc, struct disassemble_info *info, long given) break; case 'C': - func (stream, "_"); - if (given & 0x80000) - func (stream, "f"); - if (given & 0x40000) - func (stream, "s"); - if (given & 0x20000) - func (stream, "x"); - if (given & 0x10000) - func (stream, "c"); + if ((given & 0x02000200) == 0x200) + { + const char * name; + unsigned sysm = (given & 0x004f0000) >> 16; + + sysm |= (given & 0x300) >> 4; + name = banked_regname (sysm); + + if (name != NULL) + func (stream, "%s", name); + else + func (stream, "(UNDEF: %lu)", (unsigned long) sysm); + } + else + { + func (stream, "%cPSR_", + (given & 0x00400000) ? 'S' : 'C'); + if (given & 0x80000) + func (stream, "f"); + if (given & 0x40000) + func (stream, "s"); + if (given & 0x20000) + func (stream, "x"); + if (given & 0x10000) + func (stream, "c"); + } break; case 'U': - switch (given & 0xf) + if ((given & 0xf0) == 0x60) { - case 0xf: func (stream, "sy"); break; - case 0x7: func (stream, "un"); break; - case 0xe: func (stream, "st"); break; - case 0x6: func (stream, "unst"); break; - default: - func (stream, "#%d", (int) given & 0xf); - break; + switch (given & 0xf) + { + case 0xf: func (stream, "sy"); break; + default: + func (stream, "#%d", (int) given & 0xf); + break; + } + } + else + { + const char * opt = data_barrier_option (given & 0xf); + if (opt != NULL) + func (stream, "%s", opt); + else + func (stream, "#%d", (int) given & 0xf); } break; @@ -3167,6 +3506,11 @@ print_insn_arm (bfd_vma pc, struct disassemble_info *info, long given) is_unpredictable = TRUE; /* Fall through. */ case 'r': + case 'T': + /* We want register + 1 when decoding T. */ + if (*c == 'T') + ++value; + if (c[1] == 'u') { /* Eat the 'u' character. */ @@ -3257,6 +3601,22 @@ print_insn_arm (bfd_vma pc, struct disassemble_info *info, long given) } break; + case 'R': + /* Get the PSR/banked register name. */ + { + const char * name; + unsigned sysm = (given & 0x004f0000) >> 16; + + sysm |= (given & 0x300) >> 4; + name = banked_regname (sysm); + + if (name != NULL) + func (stream, "%s", name); + else + func (stream, "(UNDEF: %lu)", (unsigned long) sysm); + } + break; + case 'V': /* 16-bit unsigned immediate from a MOVT or MOVW instruction, encoded in bits 0:11 and 15:19. */ @@ -3412,20 +3772,28 @@ print_insn_thumb16 (bfd_vma pc, struct disassemble_info *info, long given) if (started) func (stream, ", "); started = 1; - func (stream, arm_regnames[14] /* "lr" */); + func (stream, "%s", arm_regnames[14] /* "lr" */); } if (domaskpc) { if (started) func (stream, ", "); - func (stream, arm_regnames[15] /* "pc" */); + func (stream, "%s", arm_regnames[15] /* "pc" */); } func (stream, "}"); } break; + case 'W': + /* Print writeback indicator for a LDMIA. We are doing a + writeback if the base register is not in the register + mask. */ + if ((given & (1 << ((given & 0x0700) >> 8))) == 0) + func (stream, "!"); + break; + case 'b': /* Print ARM V6T2 CZB address: pc+4+6 bits. */ { @@ -3460,7 +3828,7 @@ print_insn_thumb16 (bfd_vma pc, struct disassemble_info *info, long given) { case '-': { - long reg; + bfd_vma reg; c++; while (*c >= '0' && *c <= '9') @@ -3477,17 +3845,17 @@ print_insn_thumb16 (bfd_vma pc, struct disassemble_info *info, long given) break; case 'd': - func (stream, "%ld", reg); + func (stream, "%ld", (long) reg); value_in_comment = reg; break; case 'H': - func (stream, "%ld", reg << 1); + func (stream, "%ld", (long) (reg << 1)); value_in_comment = reg << 1; break; case 'W': - func (stream, "%ld", reg << 2); + func (stream, "%ld", (long) (reg << 2)); value_in_comment = reg << 2; break; @@ -3501,7 +3869,7 @@ print_insn_thumb16 (bfd_vma pc, struct disassemble_info *info, long given) break; case 'x': - func (stream, "0x%04lx", reg); + func (stream, "0x%04lx", (long) reg); break; case 'B': @@ -3572,7 +3940,7 @@ psr_name (int regno) case 9: return "PSP"; case 16: return "PRIMASK"; case 17: return "BASEPRI"; - case 18: return "BASEPRI_MASK"; + case 18: return "BASEPRI_MAX"; case 19: return "FAULTMASK"; case 20: return "CONTROL"; default: return ""; @@ -3693,6 +4061,28 @@ print_insn_thumb32 (bfd_vma pc, struct disassemble_info *info, long given) } break; + case 'H': + { + unsigned int imm = 0; + + imm |= (given & 0x000f0000u) >> 4; + imm |= (given & 0x00000fffu) >> 0; + func (stream, "#%u", imm); + value_in_comment = imm; + } + break; + + case 'V': + { + unsigned int imm = 0; + + imm |= (given & 0x00000fffu); + imm |= (given & 0x000f0000u) >> 4; + func (stream, "#%u", imm); + value_in_comment = imm; + } + break; + case 'S': { unsigned int reg = (given & 0x0000000fu); @@ -3738,7 +4128,7 @@ print_insn_thumb32 (bfd_vma pc, struct disassemble_info *info, long given) unsigned int i12 = (given & 0x00000fff); unsigned int i8 = (given & 0x000000ff); bfd_boolean writeback = FALSE, postind = FALSE; - int offset = 0; + bfd_vma offset = 0; func (stream, "[%s", arm_regnames[Rn]); if (U) /* 12-bit positive immediate offset. */ @@ -3796,11 +4186,11 @@ print_insn_thumb32 (bfd_vma pc, struct disassemble_info *info, long given) } if (postind) - func (stream, "], #%d", offset); + func (stream, "], #%d", (int) offset); else { if (offset) - func (stream, ", #%d", offset); + func (stream, ", #%d", (int) offset); func (stream, writeback ? "]!" : "]"); } @@ -3915,7 +4305,7 @@ print_insn_thumb32 (bfd_vma pc, struct disassemble_info *info, long given) unsigned int S = (given & 0x04000000u) >> 26; unsigned int J1 = (given & 0x00002000u) >> 13; unsigned int J2 = (given & 0x00000800u) >> 11; - int offset = 0; + bfd_vma offset = 0; offset |= !S << 20; offset |= J2 << 19; @@ -3933,7 +4323,7 @@ print_insn_thumb32 (bfd_vma pc, struct disassemble_info *info, long given) unsigned int S = (given & 0x04000000u) >> 26; unsigned int I1 = (given & 0x00002000u) >> 13; unsigned int I2 = (given & 0x00000800u) >> 11; - int offset = 0; + bfd_vma offset = 0; offset |= !S << 24; offset |= !(I1 ^ S) << 23; @@ -3975,16 +4365,24 @@ print_insn_thumb32 (bfd_vma pc, struct disassemble_info *info, long given) break; case 'U': - switch (given & 0xf) + if ((given & 0xf0) == 0x60) { - case 0xf: func (stream, "sy"); break; - case 0x7: func (stream, "un"); break; - case 0xe: func (stream, "st"); break; - case 0x6: func (stream, "unst"); break; - default: - func (stream, "#%d", (int) given & 0xf); - break; + switch (given & 0xf) + { + case 0xf: func (stream, "sy"); break; + default: + func (stream, "#%d", (int) given & 0xf); + break; + } } + else + { + const char * opt = data_barrier_option (given & 0xf); + if (opt != NULL) + func (stream, "%s", opt); + else + func (stream, "#%d", (int) given & 0xf); + } break; case 'C': @@ -4000,17 +4398,44 @@ print_insn_thumb32 (bfd_vma pc, struct disassemble_info *info, long given) if (given & 0x100) func (stream, "c"); } + else if ((given & 0x20) == 0x20) + { + char const* name; + unsigned sysm = (given & 0xf00) >> 8; + + sysm |= (given & 0x30); + sysm |= (given & 0x00100000) >> 14; + name = banked_regname (sysm); + + if (name != NULL) + func (stream, "%s", name); + else + func (stream, "(UNDEF: %lu)", (unsigned long) sysm); + } else { - func (stream, psr_name (given & 0xff)); + func (stream, "%s", psr_name (given & 0xff)); } break; case 'D': - if ((given & 0xff) == 0) - func (stream, "%cPSR", (given & 0x100000) ? 'S' : 'C'); + if (((given & 0xff) == 0) + || ((given & 0x20) == 0x20)) + { + char const* name; + unsigned sm = (given & 0xf0000) >> 16; + + sm |= (given & 0x30); + sm |= (given & 0x00100000) >> 14; + name = banked_regname (sm); + + if (name != NULL) + func (stream, "%s", name); + else + func (stream, "(UNDEF: %lu)", (unsigned long) sm); + } else - func (stream, psr_name (given & 0xff)); + func (stream, "%s", psr_name (given & 0xff)); break; case '0': case '1': case '2': case '3': case '4': @@ -4033,6 +4458,10 @@ print_insn_thumb32 (bfd_vma pc, struct disassemble_info *info, long given) value_in_comment = val * 4; break; + case 'S': + if (val == 13) + is_unpredictable = TRUE; + /* Fall through. */ case 'R': if (val == 15) is_unpredictable = TRUE; @@ -4072,6 +4501,21 @@ print_insn_thumb32 (bfd_vma pc, struct disassemble_info *info, long given) } break; + case 'L': + /* PR binutils/12534 + If we have a PC relative offset in an LDRD or STRD + instructions then display the decoded address. */ + if (((given >> 16) & 0xf) == 0xf) + { + bfd_vma offset = (given & 0xff) * 4; + + if ((given & (1 << 23)) == 0) + offset = - offset; + func (stream, "\t; "); + info->print_address_func ((pc & ~3) + 4 + offset, info); + } + break; + default: abort (); } @@ -4268,7 +4712,44 @@ find_ifthen_state (bfd_vma pc, ifthen_state = 0; } -/* Try to infer the code type (Arm or Thumb) from a symbol. +/* Returns nonzero and sets *MAP_TYPE if the N'th symbol is a + mapping symbol. */ + +static int +is_mapping_symbol (struct disassemble_info *info, int n, + enum map_type *map_type) +{ + const char *name; + + name = bfd_asymbol_name (info->symtab[n]); + if (name[0] == '$' && (name[1] == 'a' || name[1] == 't' || name[1] == 'd') + && (name[2] == 0 || name[2] == '.')) + { + *map_type = ((name[1] == 'a') ? MAP_ARM + : (name[1] == 't') ? MAP_THUMB + : MAP_DATA); + return TRUE; + } + + return FALSE; +} + +/* Try to infer the code type (ARM or Thumb) from a mapping symbol. + Returns nonzero if *MAP_TYPE was set. */ + +static int +get_map_sym_type (struct disassemble_info *info, + int n, + enum map_type *map_type) +{ + /* If the symbol is in a different section, ignore it. */ + if (info->section != NULL && info->section != info->symtab[n]->section) + return FALSE; + + return is_mapping_symbol (info, n, map_type); +} + +/* Try to infer the code type (ARM or Thumb) from a non-mapping symbol. Returns nonzero if *MAP_TYPE was set. */ static int @@ -4278,26 +4759,21 @@ get_sym_code_type (struct disassemble_info *info, { elf_symbol_type *es; unsigned int type; - const char *name; + + /* If the symbol is in a different section, ignore it. */ + if (info->section != NULL && info->section != info->symtab[n]->section) + return FALSE; es = *(elf_symbol_type **)(info->symtab + n); type = ELF_ST_TYPE (es->internal_elf_sym.st_info); /* If the symbol has function type then use that. */ - if (type == STT_FUNC || type == STT_ARM_TFUNC) + if (type == STT_FUNC || type == STT_GNU_IFUNC) { - *map_type = (type == STT_ARM_TFUNC) ? MAP_THUMB : MAP_ARM; - return TRUE; - } - - /* Check for mapping symbols. */ - name = bfd_asymbol_name (info->symtab[n]); - if (name[0] == '$' && (name[1] == 'a' || name[1] == 't' || name[1] == 'd') - && (name[2] == 0 || name[2] == '.')) - { - *map_type = ((name[1] == 'a') ? MAP_ARM - : (name[1] == 't') ? MAP_THUMB - : MAP_DATA); + if (ARM_SYM_BRANCH_TYPE (&es->internal_elf_sym) == ST_BRANCH_TO_THUMB) + *map_type = MAP_THUMB; + else + *map_type = MAP_ARM; return TRUE; } @@ -4355,12 +4831,12 @@ print_insn (bfd_vma pc, struct disassemble_info *info, bfd_boolean little) long given; int status; int is_thumb = FALSE; - int is_data = (bfd_asymbol_flavour (*info->symtab) - == bfd_target_elf_flavour) ? TRUE : FALSE; + int is_data = FALSE; int little_code; unsigned int size = 4; void (*printer) (bfd_vma, struct disassemble_info *, long); bfd_boolean found = FALSE; + struct arm_private_data *private_data; if (info->disassembler_options) { @@ -4373,7 +4849,7 @@ print_insn (bfd_vma pc, struct disassemble_info *info, bfd_boolean little) /* PR 10288: Control which instructions will be disassembled. */ if (info->private_data == NULL) { - static arm_feature_set features; + static struct arm_private_data private; if ((info->flags & USER_SPECIFIED_MACHINE_TYPE) == 0) /* If the user did not use the -m command line switch then default to @@ -4399,75 +4875,144 @@ print_insn (bfd_vma pc, struct disassemble_info *info, bfd_boolean little) /* Compute the architecture bitmask from the machine number. Note: This assumes that the machine number will not change during disassembly.... */ - select_arm_features (info->mach, & features); + select_arm_features (info->mach, & private.features); + + private.has_mapping_symbols = -1; + private.last_mapping_sym = -1; + private.last_mapping_addr = 0; - info->private_data = & features; + info->private_data = & private; } - + + private_data = info->private_data; + /* Decide if our code is going to be little-endian, despite what the function argument might say. */ little_code = ((info->endian_code == BFD_ENDIAN_LITTLE) || little); - /* First check the full symtab for a mapping symbol, even if there - are no usable non-mapping symbols for this address. */ + /* For ELF, consult the symbol table to determine what kind of code + or data we have. */ if (info->symtab_size != 0 && bfd_asymbol_flavour (*info->symtab) == bfd_target_elf_flavour) { bfd_vma addr; - int n; + int n, start; int last_sym = -1; - enum map_type type = MAP_DATA; + enum map_type type = MAP_ARM; - if (pc <= last_mapping_addr) - last_mapping_sym = -1; - is_thumb = (last_type == MAP_THUMB); - found = FALSE; /* Start scanning at the start of the function, or wherever we finished last time. */ - n = info->symtab_pos + 1; - if (n < last_mapping_sym) - n = last_mapping_sym; + /* PR 14006. When the address is 0 we are either at the start of the + very first function, or else the first function in a new, unlinked + executable section (eg because uf -ffunction-sections). Either way + start scanning from the beginning of the symbol table, not where we + left off last time. */ + if (pc == 0) + start = 0; + else + { + start = info->symtab_pos + 1; + if (start < private_data->last_mapping_sym) + start = private_data->last_mapping_sym; + } + found = FALSE; - /* Scan up to the location being disassembled. */ - for (; n < info->symtab_size; n++) + /* First, look for mapping symbols. */ + if (private_data->has_mapping_symbols != 0) { - addr = bfd_asymbol_value (info->symtab[n]); - if (addr > pc) - break; - if ((info->section == NULL - || info->section == info->symtab[n]->section) - && get_sym_code_type (info, n, &type)) + /* Scan up to the location being disassembled. */ + for (n = start; n < info->symtab_size; n++) + { + addr = bfd_asymbol_value (info->symtab[n]); + if (addr > pc) + break; + if (get_map_sym_type (info, n, &type)) + { + last_sym = n; + found = TRUE; + } + } + + if (!found) + { + /* No mapping symbol found at this address. Look backwards + for a preceding one. */ + for (n = start - 1; n >= 0; n--) + { + if (get_map_sym_type (info, n, &type)) + { + last_sym = n; + found = TRUE; + break; + } + } + } + + if (found) + private_data->has_mapping_symbols = 1; + + /* No mapping symbols were found. A leading $d may be + omitted for sections which start with data; but for + compatibility with legacy and stripped binaries, only + assume the leading $d if there is at least one mapping + symbol in the file. */ + if (!found && private_data->has_mapping_symbols == -1) + { + /* Look for mapping symbols, in any section. */ + for (n = 0; n < info->symtab_size; n++) + if (is_mapping_symbol (info, n, &type)) + { + private_data->has_mapping_symbols = 1; + break; + } + if (private_data->has_mapping_symbols == -1) + private_data->has_mapping_symbols = 0; + } + + if (!found && private_data->has_mapping_symbols == 1) { - last_sym = n; + type = MAP_DATA; found = TRUE; } } + /* Next search for function symbols to separate ARM from Thumb + in binaries without mapping symbols. */ if (!found) { - n = info->symtab_pos; - if (n < last_mapping_sym - 1) - n = last_mapping_sym - 1; - - /* No mapping symbol found at this address. Look backwards - for a preceeding one. */ - for (; n >= 0; n--) + /* Scan up to the location being disassembled. */ + for (n = start; n < info->symtab_size; n++) { - if ((info->section == NULL - || info->section == info->symtab[n]->section) - && get_sym_code_type (info, n, &type)) + addr = bfd_asymbol_value (info->symtab[n]); + if (addr > pc) + break; + if (get_sym_code_type (info, n, &type)) { last_sym = n; found = TRUE; - break; + } + } + + if (!found) + { + /* No mapping symbol found at this address. Look backwards + for a preceding one. */ + for (n = start - 1; n >= 0; n--) + { + if (get_sym_code_type (info, n, &type)) + { + last_sym = n; + found = TRUE; + break; + } } } } - last_mapping_sym = last_sym; - last_type = type; - is_thumb = (last_type == MAP_THUMB); - is_data = (last_type == MAP_DATA); + private_data->last_mapping_sym = last_sym; + private_data->last_type = type; + is_thumb = (private_data->last_type == MAP_THUMB); + is_data = (private_data->last_type == MAP_DATA); /* Look a little bit ahead to see if we should print out two or four bytes of data. If there's a symbol, @@ -4520,7 +5065,9 @@ print_insn (bfd_vma pc, struct disassemble_info *info, bfd_boolean little) es = *(elf_symbol_type **)(info->symbols); type = ELF_ST_TYPE (es->internal_elf_sym.st_info); - is_thumb = (type == STT_ARM_TFUNC) || (type == STT_ARM_16BIT); + is_thumb = ((ARM_SYM_BRANCH_TYPE (&es->internal_elf_sym) + == ST_BRANCH_TO_THUMB) + || type == STT_ARM_16BIT); } } @@ -4671,5 +5218,5 @@ the -M switch:\n")); regnames[i].description); fprintf (stream, " force-thumb Assume all insns are Thumb insns\n"); - fprintf (stream, " no-force-thumb Examine preceeding label to determine an insn's type\n\n"); + fprintf (stream, " no-force-thumb Examine preceding label to determine an insn's type\n\n"); }