X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=opcodes%2FChangeLog;h=ae22ba9a20b58eb15be3405f105d5e4b75eb1db0;hb=916fae91358d6167491c79c817c8a9e85ac037b9;hp=f8ea1e2e8a1ee8038e262bd230f59b5bba97547d;hpb=1d2db237d840ed479d6e725e1a7da2253f6f79b9;p=platform%2Fupstream%2Fbinutils.git diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index f8ea1e2..ae22ba9 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,448 @@ +2013-09-30 H.J. Lu + + * i386-opc.tbl: Add Size64 to movq/vmovq with Reg64 operand. + * i386-init.h: Regenerated. + +2013-09-30 Saravanan Ekanathan + + * i386-gen.c (cpu_flag_init): Add CPU_BDVER4_FLAGS. + * i386-init.h: Regenerated. + +2013-09-20 Alan Modra + + * configure: Regenerate. + +2013-09-17 Richard Sandiford + + * s390-opc.txt (clih): Make the immediate unsigned. + +2013-09-04 Roland McGrath + + PR gas/15914 + * arm-dis.c (arm_opcodes): Add udf. + (thumb_opcodes): Use "udf" mnemonic rather than UNDEFINED_INSTRUCTION. + (thumb32_opcodes): Add udf.w. + (print_insn_thumb32): Handle %H as the thumb32_opcodes comment says. + +2013-09-02 Andreas Krebbel + + * s390-opc.txt: Fix description for fiebra, fidbra, and fixbra. + For the load fp integer instructions only the suppression flag was + new with z196 version. + +2013-08-28 Nick Clifton + + * aarch64-opc.c (aarch64_logical_immediate_p): Return FALSE if the + immediate is not suitable for the 32-bit ABI. + +2013-08-23 Maciej W. Rozycki + + * micromips-opc.c (micromips_opcodes): Use RD_4 for "alnv.ps", + replacing NODS. + +2013-08-23 Yuri Chornoivan + + PR binutils/15834 + * aarch64-asm.c: Fix typos. + * aarch64-dis.c: Likewise. + * msp430-dis.c: Likewise. + +2013-08-19 Richard Sandiford + + * micromips-opc.c (micromips_opcodes): Replace "dext" and "dins" + macro entries with "dextm", "dextu", "dinsm" and "dinsu" aliases. + Use +H rather than +C for the real "dext". + * mips-opc.c (mips_builtin_opcodes): Likewise. + +2013-08-19 Richard Sandiford + + * mips-formats.h (OPTIONAL_REG, OPTIONAL_MAPPED_REG): New macros. + * micromips-opc.c (decode_micromips_operand): Use OPTIONAL_REG + and OPTIONAL_MAPPED_REG. + * mips-opc.c (decode_mips_operand): Likewise. + * mips16-opc.c (decode_mips16_operand): Likewise. + * mips-dis.c (print_insn_arg): Handle OP_OPTIONAL_REG. + +2013-08-19 H.J. Lu + + * i386-dis.c (PREFIX_EVEX_0F3A3E): Removed. + (PREFIX_EVEX_0F3A3F): Likewise. + * i386-dis-evex.h (evex_table): Updated. + +2013-08-06 Jürgen Urban + + * mips-opc.c (mips_builtin_opcodes): Add a suffixless version of + VCLIPW. + +2013-08-05 Eric Botcazou + Konrad Eisele + + * sparc-dis.c (compute_arch_mask): Set SPARC_OPCODE_ARCH_LEON bit for + bfd_mach_sparc. + * sparc-opc.c (MASK_LEON): Define. + (v6, v6notlet, v7, v8, v6notv9): Add MASK_LEON. + (letandleon): New macro. + (v9andleon): Likewise. + (sparc_opc): Add leon. + (umac): Enable for letandleon. + (smac): Likewise. + (casa): Enable for v9andleon. + (cas): Likewise. + (casl): Likewise. + +2013-08-04 Jürgen Urban + Richard Sandiford + + * mips-dis.c (print_reg): Handle OP_REG_VI, OP_REG_VF, OP_REG_R5900_I, + OP_REG_R5900_Q, OP_REG_R5900_R and OP_REG_R5900_ACC. + (print_vu0_channel): New function. + (print_insn_arg): Handle OP_VU0_SUFFIX and OP_VU0_MATCH_SUFFIX. + (print_insn_args): Handle '#'. + (print_insn_mips): Handle INSN2_VU0_CHANNEL_SUFFIX. + * mips-opc.c (mips_vu0_channel_mask): New constant. + (decode_mips_operand): Handle new VU0 operand types. + (VU0, VU0CH): New macros. + (mips_builtin_opcodes): Add VU0 opcodes. Use "+7" rather than "E" + for LQC2 and SQC2. Use "+9" rather than "G" for EE CFC2 and CTC2. + Use "+6" rather than "G" for QMFC2 and QMTC2. + +2013-08-03 Richard Sandiford + + * mips-formats.h (PCREL): Reorder parameters and update the definition + to match new mips_pcrel_operand layout. + (JUMP, JALX, BRANCH): Update accordingly. + * mips16-opc.c (decode_mips16_operand): Likewise. + +2013-08-01 Richard Sandiford + + * micromips-opc.c (WR_s): Delete. + +2013-08-01 Richard Sandiford + + * mips-opc.c (WR_1, WR_2, RD_1, RD_2, RD_3, RD_4, MOD_1, MOD_2, UDI): + New macros. + (WR_d, WR_t, WR_D, WR_T, WR_S, RD_s, RD_b, RD_t, RD_S, RD_T, RD_R) + (WR_z, WR_Z, RD_z, RD_Z, RD_d): Delete. + (mips_builtin_opcodes): Use the new position-based read-write flags + instead of field-based ones. Use UDI for "udi..." instructions. + * mips16-opc.c (WR_1, WR_2, RD_1, RD_2, RD_3, RD_4, MOD_1, MOD_2): + New macros. + (WR_x, WR_y, WR_z, WR_Y, RD_x, RD_y, RD_Z, RD_X): Delete. + (RD_T, WR_T, WR_31): Redefine using generic INSN_* flags. + (WR_SP, RD_16): New macros. + (RD_SP): Redefine as an INSN2_* flag. + (MOD_SP): Redefine in terms of RD_SP and WR_SP. + (mips16_opcodes): Use the new position-based read-write flags + instead of field-based ones. Use RD_16 for "nop". Move RD_SP to + pinfo2 field. + * micromips-opc.c (WR_1, WR_2, RD_1, RD_2, RD_3, RD_4, MOD_1, MOD_2): + New macros. + (WR_mb, RD_mc, RD_md, WR_md, RD_me, RD_mf, WR_mf, RD_mg, WR_mh, RD_mj) + (WR_mj, RD_ml, RD_mmn, RD_mp, WR_mp, RD_mq, RD_gp, WR_d, WR_t, WR_D) + (WR_T, WR_S, RD_s, RD_b, RD_t, RD_T, RD_S, RD_R, RD_D): Delete. + (RD_sp, WR_sp): Redefine to INSN2_READ_SP and INSN2_WRITE_SP. + (micromips_opcodes): Use the new position-based read-write flags + instead of field-based ones. + * mips-dis.c (print_insn_arg): Use mips_decode_reg_operand. + (print_insn_mips, print_insn_micromips): Use INSN_WRITE_1 instead + of field-based flags. + +2013-08-01 Richard Sandiford + + * mips16-opc.c (UBR, CBR, RD_31, RD_PC): Redefine as INSN2_* flags. + (WR_SP): Replace with... + (MOD_SP): ...this. + (mips16_opcodes): Update accordingly. + * mips-dis.c (print_insn_mips16): Likewise. + +2013-08-01 Richard Sandiford + + * mips16-opc.c (mips16_opcodes): Reformat. + +2013-08-01 Richard Sandiford + + * mips-opc.c (mips_builtin_opcodes): Remove WR_* and RD_* flags + for operands that are hard-coded to $0. + * micromips-opc.c (micromips_opcodes): Likewise. + +2013-08-01 Richard Sandiford + + * mips-opc.c (mips_builtin_opcodes): Use WR_31 rather than WR_d + for the single-operand forms of JALR and JALR.HB. + * micromips-opc.c (micromips_opcodes): Likewise JALR, JALRS, JALR.HB + and JALRS.HB. + +2013-08-01 Richard Sandiford + + * mips-opc.c (mips_builtin_opcodes): Add FP_D to VR5400 vector + instructions. Fix them to use WR_MACC instead of WR_CC and + add missing RD_MACCs. + +2013-08-01 Richard Sandiford + + * mips-dis.c (print_mips16_insn_arg): Include ISA bit in base address. + +2013-07-29 Peter Bergner + + * ppc-dis.c (powerpc_init_dialect): Use ppc_parse_cpu() to set dialect. + +2013-07-26 Sergey Guriev + Alexander Ivchenko + Maxim Kuznetsov + Sergey Lega + Anna Tikhonova + Ilya Tocar + Andrey Turetskiy + Ilya Verbin + Kirill Yukhin + Michael Zolotukhin + + * i386-dis-evex.h: New. + * i386-dis.c (OP_Rounding): New. + (VPCMP_Fixup): New. + (OP_Mask): New. + (Rdq): New. + (XMxmmq): New. + (EXdScalarS): New. + (EXymm): New. + (EXEvexHalfBcstXmmq): New. + (EXxmm_mdq): New. + (EXEvexXGscat): New. + (EXEvexXNoBcst): New. + (VPCMP): New. + (EXxEVexR): New. + (EXxEVexS): New. + (XMask): New. + (MaskG): New. + (MaskE): New. + (MaskR): New. + (MaskVex): New. + (modes enum): Add evex_x_gscat_mode, evex_x_nobcst_mode, + evex_half_bcst_xmmq_mode, xmm_mdq_mode, ymm_mode, + evex_rounding_mode, evex_sae_mode, mask_mode. + (USE_EVEX_TABLE): New. + (EVEX_TABLE): New. + (EVEX enum): New. + (REG enum): Add REG_EVEX_0F72, REG_EVEX_0F73, REG_EVEX_0F38C6, + REG_EVEX_0F38C7. + (MOD enum): Add MOD_EVEX_0F10_PREFIX_1, MOD_EVEX_0F10_PREFIX_3, + MOD_EVEX_0F11_PREFIX_1, MOD_EVEX_0F11_PREFIX_3, + MOD_EVEX_0F12_PREFIX_0, MOD_EVEX_0F16_PREFIX_0, MOD_EVEX_0F38C6_REG_1, + MOD_EVEX_0F38C6_REG_2, MOD_EVEX_0F38C6_REG_5, MOD_EVEX_0F38C6_REG_6, + MOD_EVEX_0F38C7_REG_1, MOD_EVEX_0F38C7_REG_2, MOD_EVEX_0F38C7_REG_5, + MOD_EVEX_0F38C7_REG_6. + (PREFIX enum): Add PREFIX_VEX_0F41, PREFIX_VEX_0F42, PREFIX_VEX_0F44, + PREFIX_VEX_0F45, PREFIX_VEX_0F46, PREFIX_VEX_0F47, PREFIX_VEX_0F4B, + PREFIX_VEX_0F90, PREFIX_VEX_0F91, PREFIX_VEX_0F92, PREFIX_VEX_0F93, + PREFIX_VEX_0F98, PREFIX_VEX_0F3A30, PREFIX_VEX_0F3A32, + PREFIX_VEX_0F3AF0, PREFIX_EVEX_0F10, PREFIX_EVEX_0F11, + PREFIX_EVEX_0F12, PREFIX_EVEX_0F13, PREFIX_EVEX_0F14, + PREFIX_EVEX_0F15, PREFIX_EVEX_0F16, PREFIX_EVEX_0F17, + PREFIX_EVEX_0F28, PREFIX_EVEX_0F29, PREFIX_EVEX_0F2A, + PREFIX_EVEX_0F2B, PREFIX_EVEX_0F2C, PREFIX_EVEX_0F2D, + PREFIX_EVEX_0F2E, PREFIX_EVEX_0F2F, PREFIX_EVEX_0F51, + PREFIX_EVEX_0F58, PREFIX_EVEX_0F59, PREFIX_EVEX_0F5A, + PREFIX_EVEX_0F5B, PREFIX_EVEX_0F5C, PREFIX_EVEX_0F5D, + PREFIX_EVEX_0F5E, PREFIX_EVEX_0F5F, PREFIX_EVEX_0F62, + PREFIX_EVEX_0F66, PREFIX_EVEX_0F6A, PREFIX_EVEX_0F6C, + PREFIX_EVEX_0F6D, PREFIX_EVEX_0F6E, PREFIX_EVEX_0F6F, + PREFIX_EVEX_0F70, PREFIX_EVEX_0F72_REG_0, PREFIX_EVEX_0F72_REG_1, + PREFIX_EVEX_0F72_REG_2, PREFIX_EVEX_0F72_REG_4, + PREFIX_EVEX_0F72_REG_6, PREFIX_EVEX_0F73_REG_2, + PREFIX_EVEX_0F73_REG_6, PREFIX_EVEX_0F76, PREFIX_EVEX_0F78, + PREFIX_EVEX_0F79, PREFIX_EVEX_0F7A, PREFIX_EVEX_0F7B, + PREFIX_EVEX_0F7E, PREFIX_EVEX_0F7F, PREFIX_EVEX_0FC2, + PREFIX_EVEX_0FC6, PREFIX_EVEX_0FD2, PREFIX_EVEX_0FD3, + PREFIX_EVEX_0FD4, PREFIX_EVEX_0FD6, PREFIX_EVEX_0FDB, + PREFIX_EVEX_0FDF, PREFIX_EVEX_0FE2, PREFIX_EVEX_0FE6 PREFIX_EVEX_0FE7, + PREFIX_EVEX_0FEB, PREFIX_EVEX_0FEF, PREFIX_EVEX_0FF2, + PREFIX_EVEX_0FF3, PREFIX_EVEX_0FF4, PREFIX_EVEX_0FFA, PREFIX_EVEX_0FFB, + PREFIX_EVEX_0FFE, PREFIX_EVEX_0F380C, PREFIX_EVEX_0F380D, + PREFIX_EVEX_0F3811, PREFIX_EVEX_0F3812, PREFIX_EVEX_0F3813, + PREFIX_EVEX_0F3814, PREFIX_EVEX_0F3815, PREFIX_EVEX_0F3816, + PREFIX_EVEX_0F3818, PREFIX_EVEX_0F3819, PREFIX_EVEX_0F381A, + PREFIX_EVEX_0F381B, PREFIX_EVEX_0F381E, PREFIX_EVEX_0F381F, + PREFIX_EVEX_0F3821, PREFIX_EVEX_0F3822, PREFIX_EVEX_0F3823, + PREFIX_EVEX_0F3824, PREFIX_EVEX_0F3825, PREFIX_EVEX_0F3827, + PREFIX_EVEX_0F3828, PREFIX_EVEX_0F3829, PREFIX_EVEX_0F382A, + PREFIX_EVEX_0F382C, PREFIX_EVEX_0F382D, PREFIX_EVEX_0F3831, + PREFIX_EVEX_0F3832, PREFIX_EVEX_0F3833, PREFIX_EVEX_0F3834, + PREFIX_EVEX_0F3835, PREFIX_EVEX_0F3836, PREFIX_EVEX_0F3837, + PREFIX_EVEX_0F3839, PREFIX_EVEX_0F383A, PREFIX_EVEX_0F383B, + PREFIX_EVEX_0F383D, PREFIX_EVEX_0F383F, PREFIX_EVEX_0F3840, + PREFIX_EVEX_0F3842, PREFIX_EVEX_0F3843, PREFIX_EVEX_0F3844, + PREFIX_EVEX_0F3845, PREFIX_EVEX_0F3846, PREFIX_EVEX_0F3847, + PREFIX_EVEX_0F384C, PREFIX_EVEX_0F384D, PREFIX_EVEX_0F384E, + PREFIX_EVEX_0F384F, PREFIX_EVEX_0F3858, PREFIX_EVEX_0F3859, + PREFIX_EVEX_0F385A, PREFIX_EVEX_0F385B, PREFIX_EVEX_0F3864, + PREFIX_EVEX_0F3865, PREFIX_EVEX_0F3876, PREFIX_EVEX_0F3877, + PREFIX_EVEX_0F387C, PREFIX_EVEX_0F387E, PREFIX_EVEX_0F387F, + PREFIX_EVEX_0F3888, PREFIX_EVEX_0F3889, PREFIX_EVEX_0F388A, + PREFIX_EVEX_0F388B, PREFIX_EVEX_0F3890, PREFIX_EVEX_0F3891, + PREFIX_EVEX_0F3892, PREFIX_EVEX_0F3893, PREFIX_EVEX_0F3896, + PREFIX_EVEX_0F3897, PREFIX_EVEX_0F3898, PREFIX_EVEX_0F3899, + PREFIX_EVEX_0F389A, PREFIX_EVEX_0F389B, PREFIX_EVEX_0F389C, + PREFIX_EVEX_0F389D, PREFIX_EVEX_0F389E, PREFIX_EVEX_0F389F, + PREFIX_EVEX_0F38A0, PREFIX_EVEX_0F38A1, PREFIX_EVEX_0F38A2, + PREFIX_EVEX_0F38A3, PREFIX_EVEX_0F38A6, PREFIX_EVEX_0F38A7, + PREFIX_EVEX_0F38A8, PREFIX_EVEX_0F38A9, PREFIX_EVEX_0F38AA, + PREFIX_EVEX_0F38AB, PREFIX_EVEX_0F38AC, PREFIX_EVEX_0F38AD, + PREFIX_EVEX_0F38AE, PREFIX_EVEX_0F38AF, PREFIX_EVEX_0F38B6, + PREFIX_EVEX_0F38B7, PREFIX_EVEX_0F38B8, PREFIX_EVEX_0F38B9, + PREFIX_EVEX_0F38BA, PREFIX_EVEX_0F38BB, PREFIX_EVEX_0F38BC, + PREFIX_EVEX_0F38BD, PREFIX_EVEX_0F38BE, PREFIX_EVEX_0F38BF, + PREFIX_EVEX_0F38C4, PREFIX_EVEX_0F38C6_REG_1, + PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5, + PREFIX_EVEX_0F38C6_REG_6, PREFIX_EVEX_0F38C7_REG_1, + PREFIX_EVEX_0F38C7_REG_2, PREFIX_EVEX_0F38C7_REG_5, + PREFIX_EVEX_0F38C7_REG_6, PREFIX_EVEX_0F38C8, PREFIX_EVEX_0F38CA, + PREFIX_EVEX_0F38CB, PREFIX_EVEX_0F38CC, PREFIX_EVEX_0F38CD, + PREFIX_EVEX_0F3A00, PREFIX_EVEX_0F3A01, PREFIX_EVEX_0F3A03, + PREFIX_EVEX_0F3A04, PREFIX_EVEX_0F3A05, PREFIX_EVEX_0F3A08, + PREFIX_EVEX_0F3A09, PREFIX_EVEX_0F3A0A, PREFIX_EVEX_0F3A0B, + PREFIX_EVEX_0F3A17, PREFIX_EVEX_0F3A18, PREFIX_EVEX_0F3A19, + PREFIX_EVEX_0F3A1A, PREFIX_EVEX_0F3A1B, PREFIX_EVEX_0F3A1D, + PREFIX_EVEX_0F3A1E, PREFIX_EVEX_0F3A1F, PREFIX_EVEX_0F3A21, + PREFIX_EVEX_0F3A23, PREFIX_EVEX_0F3A25, PREFIX_EVEX_0F3A26, + PREFIX_EVEX_0F3A27, PREFIX_EVEX_0F3A38, PREFIX_EVEX_0F3A39, + PREFIX_EVEX_0F3A3A, PREFIX_EVEX_0F3A3B, PREFIX_EVEX_0F3A3E, + PREFIX_EVEX_0F3A3F, PREFIX_EVEX_0F3A43, PREFIX_EVEX_0F3A54, + PREFIX_EVEX_0F3A55. + (VEX_LEN enum): Add VEX_LEN_0F41_P_0, VEX_LEN_0F42_P_0, VEX_LEN_0F44_P_0, + VEX_LEN_0F45_P_0, VEX_LEN_0F46_P_0, VEX_LEN_0F47_P_0, + VEX_LEN_0F4B_P_2, VEX_LEN_0F90_P_0, VEX_LEN_0F91_P_0, + VEX_LEN_0F92_P_0, VEX_LEN_0F93_P_0, VEX_LEN_0F98_P_0, + VEX_LEN_0F3A30_P_2, VEX_LEN_0F3A32_P_2, VEX_W_0F41_P_0_LEN_1, + VEX_W_0F42_P_0_LEN_1, VEX_W_0F44_P_0_LEN_0, VEX_W_0F45_P_0_LEN_1, + VEX_W_0F46_P_0_LEN_1, VEX_W_0F47_P_0_LEN_1, VEX_W_0F4B_P_2_LEN_1, + VEX_W_0F90_P_0_LEN_0, VEX_W_0F91_P_0_LEN_0, VEX_W_0F92_P_0_LEN_0, + VEX_W_0F93_P_0_LEN_0, VEX_W_0F98_P_0_LEN_0, VEX_W_0F3A30_P_2_LEN_0, + VEX_W_0F3A32_P_2_LEN_0. + (VEX_W enum): Add EVEX_W_0F10_P_0, EVEX_W_0F10_P_1_M_0, + EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_2, EVEX_W_0F10_P_3_M_0, + EVEX_W_0F10_P_3_M_1, EVEX_W_0F11_P_0, EVEX_W_0F11_P_1_M_0, + EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_2, EVEX_W_0F11_P_3_M_0, + EVEX_W_0F11_P_3_M_1, EVEX_W_0F12_P_0_M_0, EVEX_W_0F12_P_0_M_1, + EVEX_W_0F12_P_1, EVEX_W_0F12_P_2, EVEX_W_0F12_P_3, EVEX_W_0F13_P_0, + EVEX_W_0F13_P_2, EVEX_W_0F14_P_0, EVEX_W_0F14_P_2, EVEX_W_0F15_P_0, + EVEX_W_0F15_P_2, EVEX_W_0F16_P_0_M_0, EVEX_W_0F16_P_0_M_1, + EVEX_W_0F16_P_1, EVEX_W_0F16_P_2, EVEX_W_0F17_P_0, EVEX_W_0F17_P_2, + EVEX_W_0F28_P_0, EVEX_W_0F28_P_2, EVEX_W_0F29_P_0, EVEX_W_0F29_P_2, + EVEX_W_0F2A_P_1, EVEX_W_0F2A_P_3, EVEX_W_0F2B_P_0, EVEX_W_0F2B_P_2, + EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2, EVEX_W_0F2F_P_0, EVEX_W_0F2F_P_2, + EVEX_W_0F51_P_0, EVEX_W_0F51_P_1, EVEX_W_0F51_P_2, EVEX_W_0F51_P_3, + EVEX_W_0F58_P_0, EVEX_W_0F58_P_1, EVEX_W_0F58_P_2, EVEX_W_0F58_P_3, + EVEX_W_0F59_P_0, EVEX_W_0F59_P_1, EVEX_W_0F59_P_2, EVEX_W_0F59_P_3, + EVEX_W_0F5A_P_0, EVEX_W_0F5A_P_1, EVEX_W_0F5A_P_2, EVEX_W_0F5A_P_3, + EVEX_W_0F5B_P_0, EVEX_W_0F5B_P_1, EVEX_W_0F5B_P_2, EVEX_W_0F5C_P_0, + EVEX_W_0F5C_P_1, EVEX_W_0F5C_P_2, EVEX_W_0F5C_P_3, EVEX_W_0F5D_P_0, + EVEX_W_0F5D_P_1, EVEX_W_0F5D_P_2, EVEX_W_0F5D_P_3, EVEX_W_0F5E_P_0, + EVEX_W_0F5E_P_1, EVEX_W_0F5E_P_2, EVEX_W_0F5E_P_3, EVEX_W_0F5F_P_0, + EVEX_W_0F5F_P_1, EVEX_W_0F5F_P_2, EVEX_W_0F5F_P_3, EVEX_W_0F62_P_2, + EVEX_W_0F66_P_2, EVEX_W_0F6A_P_2, EVEX_W_0F6C_P_2, EVEX_W_0F6D_P_2, + EVEX_W_0F6E_P_2, EVEX_W_0F6F_P_1, EVEX_W_0F6F_P_2, EVEX_W_0F70_P_2, + EVEX_W_0F72_R_2_P_2, EVEX_W_0F72_R_6_P_2, EVEX_W_0F73_R_2_P_2, + EVEX_W_0F73_R_6_P_2, EVEX_W_0F76_P_2, EVEX_W_0F78_P_0, + EVEX_W_0F79_P_0, EVEX_W_0F7A_P_1, EVEX_W_0F7A_P_3, EVEX_W_0F7B_P_1, + EVEX_W_0F7B_P_3, EVEX_W_0F7E_P_1, EVEX_W_0F7E_P_2, EVEX_W_0F7F_P_1, + EVEX_W_0F7F_P_2, EVEX_W_0FC2_P_0, EVEX_W_0FC2_P_1, EVEX_W_0FC2_P_2, + EVEX_W_0FC2_P_3, EVEX_W_0FC6_P_0, EVEX_W_0FC6_P_2, EVEX_W_0FD2_P_2, + EVEX_W_0FD3_P_2, EVEX_W_0FD4_P_2, EVEX_W_0FD6_P_2, EVEX_W_0FE6_P_1, + EVEX_W_0FE6_P_2, EVEX_W_0FE6_P_3, EVEX_W_0FE7_P_2, EVEX_W_0FF2_P_2, + EVEX_W_0FF3_P_2, EVEX_W_0FF4_P_2, EVEX_W_0FFA_P_2, EVEX_W_0FFB_P_2, + EVEX_W_0FFE_P_2, EVEX_W_0F380C_P_2, EVEX_W_0F380D_P_2, + EVEX_W_0F3811_P_1, EVEX_W_0F3812_P_1, EVEX_W_0F3813_P_1, + EVEX_W_0F3813_P_2, EVEX_W_0F3814_P_1, EVEX_W_0F3815_P_1, + EVEX_W_0F3818_P_2, EVEX_W_0F3819_P_2, EVEX_W_0F381A_P_2, + EVEX_W_0F381B_P_2, EVEX_W_0F381E_P_2, EVEX_W_0F381F_P_2, + EVEX_W_0F3821_P_1, EVEX_W_0F3822_P_1, EVEX_W_0F3823_P_1, + EVEX_W_0F3824_P_1, EVEX_W_0F3825_P_1, EVEX_W_0F3825_P_2, + EVEX_W_0F3828_P_2, EVEX_W_0F3829_P_2, EVEX_W_0F382A_P_1, + EVEX_W_0F382A_P_2, EVEX_W_0F3831_P_1, EVEX_W_0F3832_P_1, + EVEX_W_0F3833_P_1, EVEX_W_0F3834_P_1, EVEX_W_0F3835_P_1, + EVEX_W_0F3835_P_2, EVEX_W_0F3837_P_2, EVEX_W_0F383A_P_1, + EVEX_W_0F3840_P_2, EVEX_W_0F3858_P_2, EVEX_W_0F3859_P_2, + EVEX_W_0F385A_P_2, EVEX_W_0F385B_P_2, EVEX_W_0F3891_P_2, + EVEX_W_0F3893_P_2, EVEX_W_0F38A1_P_2, EVEX_W_0F38A3_P_2, + EVEX_W_0F38C7_R_1_P_2, EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2, + EVEX_W_0F38C7_R_6_P_2, EVEX_W_0F3A00_P_2, EVEX_W_0F3A01_P_2, + EVEX_W_0F3A04_P_2, EVEX_W_0F3A05_P_2, EVEX_W_0F3A08_P_2, + EVEX_W_0F3A09_P_2, EVEX_W_0F3A0A_P_2, EVEX_W_0F3A0B_P_2, + EVEX_W_0F3A18_P_2, EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2, + EVEX_W_0F3A1B_P_2, EVEX_W_0F3A1D_P_2, EVEX_W_0F3A21_P_2, + EVEX_W_0F3A23_P_2, EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2, + EVEX_W_0F3A3A_P_2, EVEX_W_0F3A3B_P_2, EVEX_W_0F3A43_P_2. + (struct vex): Add fields evex, r, v, mask_register_specifier, + zeroing, ll, b. + (intel_names_xmm): Add upper 16 registers. + (att_names_xmm): Ditto. + (intel_names_ymm): Ditto. + (att_names_ymm): Ditto. + (names_zmm): New. + (intel_names_zmm): Ditto. + (att_names_zmm): Ditto. + (names_mask): Ditto. + (intel_names_mask): Ditto. + (att_names_mask): Ditto. + (names_rounding): Ditto. + (names_broadcast): Ditto. + (x86_64_table): Add escape to evex-table. + (reg_table): Include reg_table evex-entries from + i386-dis-evex.h. Fix prefetchwt1 instruction. + (prefix_table): Add entries for new instructions. + (vex_table): Ditto. + (vex_len_table): Ditto. + (vex_w_table): Ditto. + (mod_table): Ditto. + (get_valid_dis386): Properly handle new instructions. + (print_insn): Handle zmm and mask registers, print mask operand. + (intel_operand_size): Support EVEX, new modes and sizes. + (OP_E_register): Handle new modes. + (OP_E_memory): Ditto. + (OP_G): Ditto. + (OP_XMM): Ditto. + (OP_EX): Ditto. + (OP_VEX): Ditto. + * i386-gen.c (cpu_flag_init): Update CPU_ANY_SSE_FLAGS and + CPU_ANY_AVX_FLAGS. Add CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS, + CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS. + (cpu_flags): Add CpuAVX512F, CpuAVX512CD, CpuAVX512ER, + CpuAVX512PF and CpuVREX. + (operand_type_init): Add OPERAND_TYPE_REGZMM, + OPERAND_TYPE_REGMASK and OPERAND_TYPE_VEC_DISP8. + (opcode_modifiers): Add EVex, Masking, VecESize, Broadcast, + StaticRounding, SAE, Disp8MemShift, NoDefMask. + (operand_types): Add RegZMM, RegMask, Vec_Disp8, Zmmword. + * i386-init.h: Regenerate. + * i386-opc.h (CpuAVX512F): New. + (CpuAVX512CD): New. + (CpuAVX512ER): New. + (CpuAVX512PF): New. + (CpuVREX): New. + (i386_cpu_flags): Add cpuavx512f, cpuavx512cd, cpuavx512er, + cpuavx512pf and cpuvrex fields. + (VecSIB): Add VecSIB512. + (EVex): New. + (Masking): New. + (VecESize): New. + (Broadcast): New. + (StaticRounding): New. + (SAE): New. + (Disp8MemShift): New. + (NoDefMask): New. + (i386_opcode_modifier): Add evex, masking, vecesize, broadcast, + staticrounding, sae, disp8memshift and nodefmask. + (RegZMM): New. + (Zmmword): Ditto. + (Vec_Disp8): Ditto. + (i386_operand_type): Add regzmm, regmask, zmmword and vec_disp8 + fields. + (RegVRex): New. + * i386-opc.tbl: Add AVX512 instructions. + * i386-reg.tbl: Add 16 upper XMM and YMM registers, 32 new ZMM + registers, mask registers. + * i386-tbl.h: Regenerate. + 2013-07-25 Aaro Koskinen PR gas/15220