X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=opcodes%2FChangeLog;h=ae22ba9a20b58eb15be3405f105d5e4b75eb1db0;hb=916fae91358d6167491c79c817c8a9e85ac037b9;hp=5668f34f0b1b477d2cf8d4f6e4209846a888a7bf;hpb=a8d92fc6c3eaea4a92b0c52ecf77fe115ff87c51;p=platform%2Fupstream%2Fbinutils.git diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index 5668f34..ae22ba9 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,160 @@ +2013-09-30 H.J. Lu + + * i386-opc.tbl: Add Size64 to movq/vmovq with Reg64 operand. + * i386-init.h: Regenerated. + +2013-09-30 Saravanan Ekanathan + + * i386-gen.c (cpu_flag_init): Add CPU_BDVER4_FLAGS. + * i386-init.h: Regenerated. + +2013-09-20 Alan Modra + + * configure: Regenerate. + +2013-09-17 Richard Sandiford + + * s390-opc.txt (clih): Make the immediate unsigned. + +2013-09-04 Roland McGrath + + PR gas/15914 + * arm-dis.c (arm_opcodes): Add udf. + (thumb_opcodes): Use "udf" mnemonic rather than UNDEFINED_INSTRUCTION. + (thumb32_opcodes): Add udf.w. + (print_insn_thumb32): Handle %H as the thumb32_opcodes comment says. + +2013-09-02 Andreas Krebbel + + * s390-opc.txt: Fix description for fiebra, fidbra, and fixbra. + For the load fp integer instructions only the suppression flag was + new with z196 version. + +2013-08-28 Nick Clifton + + * aarch64-opc.c (aarch64_logical_immediate_p): Return FALSE if the + immediate is not suitable for the 32-bit ABI. + +2013-08-23 Maciej W. Rozycki + + * micromips-opc.c (micromips_opcodes): Use RD_4 for "alnv.ps", + replacing NODS. + +2013-08-23 Yuri Chornoivan + + PR binutils/15834 + * aarch64-asm.c: Fix typos. + * aarch64-dis.c: Likewise. + * msp430-dis.c: Likewise. + +2013-08-19 Richard Sandiford + + * micromips-opc.c (micromips_opcodes): Replace "dext" and "dins" + macro entries with "dextm", "dextu", "dinsm" and "dinsu" aliases. + Use +H rather than +C for the real "dext". + * mips-opc.c (mips_builtin_opcodes): Likewise. + +2013-08-19 Richard Sandiford + + * mips-formats.h (OPTIONAL_REG, OPTIONAL_MAPPED_REG): New macros. + * micromips-opc.c (decode_micromips_operand): Use OPTIONAL_REG + and OPTIONAL_MAPPED_REG. + * mips-opc.c (decode_mips_operand): Likewise. + * mips16-opc.c (decode_mips16_operand): Likewise. + * mips-dis.c (print_insn_arg): Handle OP_OPTIONAL_REG. + +2013-08-19 H.J. Lu + + * i386-dis.c (PREFIX_EVEX_0F3A3E): Removed. + (PREFIX_EVEX_0F3A3F): Likewise. + * i386-dis-evex.h (evex_table): Updated. + +2013-08-06 Jürgen Urban + + * mips-opc.c (mips_builtin_opcodes): Add a suffixless version of + VCLIPW. + +2013-08-05 Eric Botcazou + Konrad Eisele + + * sparc-dis.c (compute_arch_mask): Set SPARC_OPCODE_ARCH_LEON bit for + bfd_mach_sparc. + * sparc-opc.c (MASK_LEON): Define. + (v6, v6notlet, v7, v8, v6notv9): Add MASK_LEON. + (letandleon): New macro. + (v9andleon): Likewise. + (sparc_opc): Add leon. + (umac): Enable for letandleon. + (smac): Likewise. + (casa): Enable for v9andleon. + (cas): Likewise. + (casl): Likewise. + +2013-08-04 Jürgen Urban + Richard Sandiford + + * mips-dis.c (print_reg): Handle OP_REG_VI, OP_REG_VF, OP_REG_R5900_I, + OP_REG_R5900_Q, OP_REG_R5900_R and OP_REG_R5900_ACC. + (print_vu0_channel): New function. + (print_insn_arg): Handle OP_VU0_SUFFIX and OP_VU0_MATCH_SUFFIX. + (print_insn_args): Handle '#'. + (print_insn_mips): Handle INSN2_VU0_CHANNEL_SUFFIX. + * mips-opc.c (mips_vu0_channel_mask): New constant. + (decode_mips_operand): Handle new VU0 operand types. + (VU0, VU0CH): New macros. + (mips_builtin_opcodes): Add VU0 opcodes. Use "+7" rather than "E" + for LQC2 and SQC2. Use "+9" rather than "G" for EE CFC2 and CTC2. + Use "+6" rather than "G" for QMFC2 and QMTC2. + +2013-08-03 Richard Sandiford + + * mips-formats.h (PCREL): Reorder parameters and update the definition + to match new mips_pcrel_operand layout. + (JUMP, JALX, BRANCH): Update accordingly. + * mips16-opc.c (decode_mips16_operand): Likewise. + +2013-08-01 Richard Sandiford + + * micromips-opc.c (WR_s): Delete. + +2013-08-01 Richard Sandiford + + * mips-opc.c (WR_1, WR_2, RD_1, RD_2, RD_3, RD_4, MOD_1, MOD_2, UDI): + New macros. + (WR_d, WR_t, WR_D, WR_T, WR_S, RD_s, RD_b, RD_t, RD_S, RD_T, RD_R) + (WR_z, WR_Z, RD_z, RD_Z, RD_d): Delete. + (mips_builtin_opcodes): Use the new position-based read-write flags + instead of field-based ones. Use UDI for "udi..." instructions. + * mips16-opc.c (WR_1, WR_2, RD_1, RD_2, RD_3, RD_4, MOD_1, MOD_2): + New macros. + (WR_x, WR_y, WR_z, WR_Y, RD_x, RD_y, RD_Z, RD_X): Delete. + (RD_T, WR_T, WR_31): Redefine using generic INSN_* flags. + (WR_SP, RD_16): New macros. + (RD_SP): Redefine as an INSN2_* flag. + (MOD_SP): Redefine in terms of RD_SP and WR_SP. + (mips16_opcodes): Use the new position-based read-write flags + instead of field-based ones. Use RD_16 for "nop". Move RD_SP to + pinfo2 field. + * micromips-opc.c (WR_1, WR_2, RD_1, RD_2, RD_3, RD_4, MOD_1, MOD_2): + New macros. + (WR_mb, RD_mc, RD_md, WR_md, RD_me, RD_mf, WR_mf, RD_mg, WR_mh, RD_mj) + (WR_mj, RD_ml, RD_mmn, RD_mp, WR_mp, RD_mq, RD_gp, WR_d, WR_t, WR_D) + (WR_T, WR_S, RD_s, RD_b, RD_t, RD_T, RD_S, RD_R, RD_D): Delete. + (RD_sp, WR_sp): Redefine to INSN2_READ_SP and INSN2_WRITE_SP. + (micromips_opcodes): Use the new position-based read-write flags + instead of field-based ones. + * mips-dis.c (print_insn_arg): Use mips_decode_reg_operand. + (print_insn_mips, print_insn_micromips): Use INSN_WRITE_1 instead + of field-based flags. + +2013-08-01 Richard Sandiford + + * mips16-opc.c (UBR, CBR, RD_31, RD_PC): Redefine as INSN2_* flags. + (WR_SP): Replace with... + (MOD_SP): ...this. + (mips16_opcodes): Update accordingly. + * mips-dis.c (print_insn_mips16): Likewise. + 2013-08-01 Richard Sandiford * mips16-opc.c (mips16_opcodes): Reformat.