X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=opcodes%2FChangeLog;h=9a80d0481b907ddff78ba394abc84f494536b080;hb=b015e599c772eeb5f818d710119ee43e7df0feff;hp=6efdab07c8132504b665bfdbe1ea62787434f74c;hpb=a1ccaec9526b7c2ebd2cc4fc5b5367389dc729ec;p=platform%2Fupstream%2Fbinutils.git diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index 6efdab0..9a80d04 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,175 @@ +2013-05-09 Andrew Pinski + + * mips-dis.c (mips_arch_choices): Add INSN_VIRT to mips32r2. + Add INSN_VIRT and INSN_VIRT64 to mips64r2. + (parse_mips_dis_option): Handle the virt option. + (print_insn_args): Handle "+J". + (print_mips_disassembler_options): Print out message about virt64. + * mips-opc.c (IVIRT): New define. + (IVIRT64): New define. + (mips_builtin_opcodes): Add dmfgc0, dmtgc0, hypcall, mfgc0, mtgc0, + tlbgr, tlbgwi, tlbginv, tlbginvf, tlbgwr, tlbgp VIRT instructions. + Move rfe to the bottom as it conflicts with tlbgp. + +2013-05-09 Alan Modra + + * ppc-opc.c (extract_vlesi): Properly sign extend. + (extract_vlensi): Likewise. Comment reason for setting invalid. + +2013-05-02 Nick Clifton + + * msp430-dis.c: Add support for MSP430X instructions. + +2013-04-24 Sandra Loosemore + + * nios2-opc.c (nios2_builtin_reg): Rename "fstatus" control register + to "eccinj". + +2013-04-17 Wei-chen Wang + + PR binutils/15369 + * cgen-dis.c (hash_insn_array): Use CGEN_CPU_INSN_ENDIAN instead + of CGEN_CPU_ENDIAN. + (hash_insns_list): Likewise. + +2013-04-10 Jan Kratochvil + + * rl78-dis.c (print_insn_rl78): Use alternative form as a GCC false + warning workaround. + +2013-04-08 Jan Beulich + + * i386-opc.tbl: Fold 64-bit and non-64-bit jecxz entries. + * i386-tbl.h: Re-generate. + +2013-04-06 David S. Miller + + * sparc-dis.c (compare_opcodes): When encountering multiple aliases + of an opcode, prefer the one with F_PREFERRED set. + * sparc-opc.c (sparc_opcodes): Add ldtw, ldtwa, sttw, sttwa, + lzcnt, flush with '[address]' syntax, and missing cbcond pseudo + ops. Make 64-bit VIS logical ops have "d" suffix in their names, + mark existing mnenomics as aliases. Add "cc" suffix to edge + instructions generating condition codes, mark existing mnenomics + as aliases. Add "fp" prefix to VIS compare instructions, mark + existing mnenomics as aliases. + +2013-04-03 Nick Clifton + + * v850-dis.c (print_value): With V850_INVERSE_PCREL compute the + destination address by subtracting the operand from the current + address. + * v850-opc.c (insert_u16_loop): Disallow negative offsets. Store + a positive value in the insn. + (extract_u16_loop): Do not negate the returned value. + (D16_LOOP): Add V850_INVERSE_PCREL flag. + + (ceilf.sw): Remove duplicate entry. + (cvtf.hs): New entry. + (cvtf.sh): Likewise. + (fmaf.s): Likewise. + (fmsf.s): Likewise. + (fnmaf.s): Likewise. + (fnmsf.s): Likewise. + (maddf.s): Restrict to E3V5 architectures. + (msubf.s): Likewise. + (nmaddf.s): Likewise. + (nmsubf.s): Likewise. + +2013-03-27 H.J. Lu + + * i386-dis.c (get_sib): Add the sizeflag argument. Properly + check address mode. + (print_insn): Pass sizeflag to get_sib. + +2013-03-27 Alexis Deruelle + + PR binutils/15068 + * tic6x-dis.c: Add support for displaying 16-bit insns. + +2013-03-20 Alexis Deruelle + + PR gas/15095 + * tic6x-dis.c (print_insn_tic6x): Decode opcodes that have + individual msb and lsb halves in src1 & src2 fields. Discard the + src1 (lsb) value and only use src2 (msb), discarding bit 0, to + follow what Ti SDK does in that case as any value in the src1 + field yields the same output with SDK disassembler. + +2013-03-12 Michael Eager + + * opcodes/mips-dis.c (print_insn_args): Modify def of reg. + +2013-03-11 Sebastian Huber + + * nios2-opc.c (nios2_builtin_opcodes): Add entry for wrprs. + +2013-03-11 Sebastian Huber + + * nios2-opc.c (nios2_builtin_opcodes): Add entry for rdprs. + +2013-03-11 Sebastian Huber + + * nios2-opc.c (nios2_builtin_regs): Add sstatus alias for ba register. + +2013-03-11 Kyrylo Tkachov + + * arm-dis.c (arm_opcodes): Add entries for CRC instructions. + (thumb32_opcodes): Likewise. + (print_insn_thumb32): Handle 'S' control char. + +2013-03-08 Yann Sionneau + + * lm32-desc.c: Regenerate. + +2013-03-01 H.J. Lu + + * i386-reg.tbl (riz): Add RegRex64. + * i386-tbl.h: Regenerated. + +2013-02-28 Yufeng Zhang + + * aarch64-tbl.h (QL_I3SAMEW, QL_I3WWX): New macros. + (aarch64_feature_crc): New static. + (CRC): New macro. + (aarch64_opcode_table): Add entries for the crc32b, crc32h, crc32w, + crc32x, crc32cb, crc32ch, crc32cw and crc32cx instructions. + * aarch64-asm-2.c: Re-generate. + * aarch64-dis-2.c: Ditto. + * aarch64-opc-2.c: Ditto. + +2013-02-27 Alan Modra + + * rl78-decode.opc (rl78_decode_opcode): Fix typo. + * rl78-decode.c: Regenerate. + +2013-02-25 Kaushik Phatak + + * rl78-decode.opc: Fix encoding of DIVWU insn. + * rl78-decode.c: Regenerate. + +2013-02-19 H.J. Lu + + PR gas/15159 + * i386-dis.c (rm_table): Add clac and stac to RM_0F01_REG_1. + + * i386-gen.c (cpu_flag_init): Add CPU_SMAP_FLAGS. + (cpu_flags): Add CpuSMAP. + + * i386-opc.h (CpuSMAP): New. + (i386_cpu_flags): Add cpusmap. + + * i386-opc.tbl: Add clac and stac. + + * i386-init.h: Regenerated. + * i386-tbl.h: Likewise. + +2013-02-15 Markos Chandras + + * metag-dis.c: Initialize outf->bytes_per_chunk to 4 + which also makes the disassembler output be in little + endian like it should be. + 2013-02-14 Yufeng Zhang * aarch64-opc.c (aarch64_prfops): Change unnamed operation 'name'